Next-generation closed-loop epilepsy management system should be able to flag both the onset and termination of the ictal phase of repeated seizures, so that the neural stimulation profile can be tailor made to align to the optimal time frame for the best therapeutic outcomes. However, the presence of stimulation artifact (SA) makes it a significant challenge in implementing such a closed-loop system which requires concurrent recording of neural signals and stimulation of certain brain regions. High dynamic range (DR) is an important requirement for neural amplifiers to ensure lossless recording. We propose a high DR, rail-to-rail artifact tolerant system-on-a-chip (SoC). In the absence of SA, the SoC records and quantifies neural signals with low power consumption. When a stimulation artifact is detected, an additional ADC and a DAC are used to sample and reconstruct the artifact signal, respectively. The reconstructed artifact is then fed to the input of a differential amplifier as a common-mode signal for artifact removal. The target neural signal can subsequently be extracted by an independent component analysis algorithm. The technique has been verified using X-Fab’s 0.18-µm CMOS process. The simulation result suggests the power consumptions with and without artifact suppression are 15.6 and 46.5 µW, respectively. The input dynamic range of the SoC can be extended to 84.9-dB when an SA is detected.

This paper presents the design of a small-sized low-noise low-power analog front-end (AFE) amplifier for implantable multi-channel neural recording applications. The proposed amplifier consists of two stages, a chopper-stabilized capacitively-coupled instrumentation amplifier (CS-CCIA) followed by a programmable-gain amplifier (PGA). The amplifier can be set in either of the two modes: AP mode (300 ~ 10 kHz for capturing action potentials) and wide-band mode (1.5 ~ 10 kHz for capturing both local field potentials and action potentials). Depending on the neural signals of interest, the amplifier’s high-pass cut-off frequency for AP and wide-band modes is set by large pseudo resistors and a dedicated DC servo loop, respectively. In contrast to most existing designs in which the low-pass cut-off frequency is set by a dedicated filter circuit after the amplifier stages, the proposed amplifier sets a gain- independent low-pass cut-off frequency within the PGA, minimizing the size of the overall analog front-end. The proposed AFE has been fabricated using a 180-nm CMOS process, occupying a small area of 0.04 mm2. It consumes 3 μW under a 1.2-V supply. The input-referred noise is measured 4 µVrms in the action potential band and 4.6 µVrms in the wide band.

Deep reinforcement learning (DRL) based cooperative adaptive cruise control (CACC) of connected and autonomous vehicles (CAVs) shows great potential in improving controllers' adaptability to real-world dynamic traffic conditions. However, most DRL-based CACCs primarily focus on fixed predecessor following (PF) information flow topology (IFT) while ignoring the heterogeneity of the vehicle. In reality, even though most CACCs separate the platoon by human-driven vehicle (HDV) while considering the HDV as the leading vehicle of the platoon, the heterogeneity of the preceding vehicle with different motion properties (i.e. HDV and CAV) still exists. The adaptability of the DRL-based CACC may be degraded if the above heterogeneity is ignored. To fill this research gap, a DRL-based CACC with preceding vehicle properties is proposed in this study. Specifically, it first designs three typical sub-controllers by considering the applicable IFTs and the properties of preceding vehicles. The proposed DRL-based CACC is established according to the aforementioned designs with the objectives of safety, efficiency, smoothness, and comfort. To enhance the efficiency of transforming acquired data into the learning experience during the exploration process of the DRL algorithm, a periodic update deep deterministic policy gradient (DDPG) algorithm is proposed. The results demonstrate the necessity of considering the preceding vehicle properties in designing the corresponding controller for a specific IFT.

Automatic myocardial segmentation of contrast echocardio-graphy has shown great potential in the quantification of myocardial perfusion parameters. Segmentation quality control is an important step to ensure the accuracy of segmentation results for quality research as well as its clinical application. Usually, the segmentation quality control happens after the data acquisition. At the data acquisition time, the operator could not know the quality of the segmentation results. On-the-fly segmentation quality control could help the operator to adjust the ultrasound probe or retake data if the quality is unsatisfied, which can greatly reduce the effort of time-consuming manual correction. However, it is infeasible to deploy state-of-the-art DNN-based models because the segmentation module and quality control module must fit in the limited hardware resource on the ultrasound machine while satisfying strict latency constraints. In this paper, we propose a hardware-aware neural architecture search framework for automatic myocardial segmentation and quality control of contrast echocardiography. We explicitly incorporate the hardware latency as a regularization term into the loss function during training. The proposed method searches the best neural network architecture for the segmentation module and quality prediction module with strict latency.

As one of the most commonly ordered imaging tests, the computed tomography (CT) scan comes with inevitable radiation exposure that increases cancer risk to patients. However, CT image quality is directly related to radiation dose, and thus it is desirable to obtain high-quality CT images with as little dose as possible. CT image denoising tries to obtain high-dose-like high-quality CT images (domain Y ) from low dose low-quality CT images (domain X ), which can be treated as an image-to-image translation task where the goal is to learn the transform between a source domain X (noisy images) and a target domain Y (clean images). Recently, the cycle-consistent adversarial denoising network (CCADN) has achieved state-of-the-art results by enforcing cycle-consistent loss without the need of paired training data, since the paired data is hard to collect due to patients’ interests and cardiac motion. However, out of concerns on patients’ privacy and data security, protocols typically require clinics to perform medical image processing tasks including CT image denoising locally (i.e., edge denoising). Therefore, the network models need to achieve high performance under various computation resource constraints including memory and performance. Our detailed analysis of CCADN raises a number of interesting questions that point to potential ways to further improve its performance using the same or even fewer computation resources. For example, if the noise is large leading to a significant difference between domain X and domain Y , can we bridge X and Y with a intermediate domain Z such that both the denoising process between X and Z and that between Z and Y are easier to learn? As such intermediate domains lead to multiple cycles, how do we best enforce cycle- consistency? Driven by these questions, we propose a multi-cycle-consistent adversarial network (MCCAN) that builds intermediate domains and enforces both local and global cycle-consistency for edge denoising of CT images. The global cycle-consistency couples all generators together to model the whole denoising process, whereas the local cycle-consistency imposes effective supervision on the process between adjacent domains. Experiments show that both local and global cycle-consistency are important for the success of MCCAN, which outperforms CCADN in terms of denoising quality with slightly less computation resource consumption.

This article explores the weight binarization of the deconvolution-based generator in a generative adversarial network (GAN) for memory saving and speedup of image construction on the edge. This article suggests that different from convolutional neural networks (including the discriminator) where all layers can be binarized, only some of the layers in the generator can be binarized without significant performance loss. Supported by theoretical analysis and verified by experiments, a direct metric based on the dimension of deconvolution operations is established, which can be used to quickly decide which layers in a generator can be binarized. Our results also indicate that both the generator and the discriminator should be binarized simultaneously for balanced competition and better performance during training. The experimental results on CelebA dataset with DCGAN and original loss functions suggest that directly applying state-of-the-art binarization techniques to all the layers of the generator will lead to 2.83× performance loss measured by sliced Wasserstein distance compared with the original generator, while applying them to selected layers only can yield up to 25.81× saving in memory consumption, and 1.96× and 1.32× speedup in inference and training, respectively, with little performance loss. Similar conclusions can also be drawn on other loss functions for different GANs.

In coal-fired power plants, it is critical to improve the operational efficiency of boilers for sustainability. In this work, we formulate real-time boiler control as an optimization problem that looks for the best distribution of temperature in different zones and oxygen content from the flue to improve the boiler's stability and energy efficiency. We employ an efficient algorithm by integrating appropriate machine learning and optimization techniques. We obtain a large dataset collected from a real boiler for more than two months from our industry partner, and conduct extensive experiments to demonstrate the effectiveness and efficiency of the proposed algorithm.