This paper presents the design and measurement results of tunable Relaxation Oscillator ($\mathbf{R x O}$) proposed in standard 65 nm CMOS technology. The proposed RxO achieves the wide oscillation frequency range with fine tunability and low power consumption. The achieved results were obtained by measuring the prototype chip and show that the proposed oscillator can be tuned within the range of 72 kHz to 123 MHz, with a tuning step below 0.77 % for digital tuning and$0.53 \% / \text{mV}$for analog tuning with respect to the absolute value of the oscillation frequency. The low power consumption from$1 \text{nW} / \text{kHz}$to$23 \text{nW} / \text{kHz}$was observed. The figure of merit of 64 dB has been found to demonstrate an excellent dynamic range with fine tunability features.

This paper presents tunable voltage reference (TVR) designed in a standard general purpose 65nm CMOS technology. Designed circuit is based on two-transistor (2T) voltage reference (VR) with digitally controlled operational amplifier (OPAMP). Developed TVR provides stable output voltage from 0.38 V to 1.1 V with non-linear tuning step under 0.5% of the output voltage (from 1.9 mV to 2.9 mV). The supply voltage in the range from 0.91 V to 1.5 V is used. The circuit offers parameter PSRR = -53.59 dB (at 1 kHz) and line regulation (LNR) of 0.35% in the worst case. The required area is 0.0185 mm2. The proposed TVR was used to precise frequency tuning of oscillator. Provided results are obtained from both simulations and measurement of the manufactured ASIC prototype.

The paper addresses a development and evaluation of well-known EKV MOS transistor model with focus on the ultra low-voltage / ultra low-power analog IC design employing rather “exotic” bulk-driven technique. The presented contribution can be viewed as an extension of already established compact simulation model with modifications to the original parameter extraction flow. The article contains a brief description of EKV model fundamentals, a novel parameter extraction flow and most importantly, the comparison of developed EKV model with the foundry-provided BSIM model (v3.3) and the experimental measurement data obtained from prototype chip samples fabricated in 130 nm CMOS technology.

The paper addresses an evaluation of dynamic properties of silicon-proven ultra low-voltage/low-power rail-to-rail comparator fabricated in general purpose 130 nm CMOS technology. The experimental results confirm a correct operation at power supply voltage of VDD= 0.4 V and good agreement with post-layout simulation results can be observed. The proposed comparator topology has been proven to work in nW range and is also capable of operation with even lower power supply voltages and without a need of post-processing trimming. The article contains incremental results of performance analysis of discussed circuitry already published in [1].

The paper addresses a novel topology of ultra low-voltage comparator with rail-to-rail input voltage range and selectable level of hysteresis designed in a standard twin-well 130 nm CMOS technology. The nominal power supply voltage of 0.4 V was used, and the working temperature range was set to the industrial standard from -20 °C to 85 °C. The proposed comparator design is intended to work in an energy harvesting system. Hence, low power consumption is the key requirement. The comparator employs bulk-driven transistors in the input stage and operates in so-called current mode. The designed comparator circuit draws less than 5 μA in typical conditions but its function and robustness have been verified across all possible process and temperature corners. The design was submitted to foundry for manufacturing and the measured data can be expected soon.

With the emergence of always-on wireless sensing nodes, AC/DC power conversion solutions for sub 1 W applications are required. Existing approaches are not efficient for such output loads, and therefore, new solutions need to be provided. In this paper, we propose a solution that is optimized for operation with output loads up to 500 mW, while high efficiency and close to zero no-load consumption have been our foremost design goals. The proposed design is implemented in a high-voltage CMOS process and transistor level simulation results show improved properties of the proposed solution over the existing ones.

This paper addresses a design and performance evaluation of ultra low-voltage non-clocked voltage comparator. The circuit was designed in a standard twin-well 130 nm CMOS technology and is intended to work in temperature range of -20 – 85 °C with the power supply voltage of 0.6 V. The proposed comparator can handle the input voltage within the rail-to-rail range. Low-voltage design approaches, namely, g m /I D design methodology in combination with the bulk-driven operation approach have been employed. The measurements on fabricated prototype chips included evaluation of both static as well as dynamic parameters. An excellent correlation between simulations and the measured bench data was observed. The proposed comparator is currently being reviewed and re-designed for even lower power supply voltage of 0.4 V.

This paper deals with the design of a RF rectifier usable for inductively powering implantable medical devices, more specifically a fully integrated on–chip device. This application has specific challenges that need to be met, mainly the weak coupling between the transmitter and receiver, which results in small input power for the rectifier. The use of an on–chip receiver coil puts restrictions on the operating frequency, which is set to 200 MHz. The input voltage is also rather low due to the low quality of on–chip circuit components. The proposed rectifier uses the differential drive cross-coupled bridge topology. A body biasing technique and triple-well NMOS transistors are used to achieve better performance at the low input voltage without the need for additional circuitry. The rectifier was designed in a 130 nm CMOS technology. Effects of the input voltage, power and load resistance on the power conversion efficiency and the output power were investigated. A significant increase in the output power was observed.