Hyperdimensional Computing (HDC) is a computationally efficient method of performing highly-accurate classification by encoding information into very wide binary vectors with simple binary operations. In this work, we explore methods of accelerating the encoding process, demonstrated on a RISC-V processor. First, we propose a bit-serial word-parallel approach to accelerate the spatial encoder, the slowest HDC block, and demonstrate its promise with a 12.6 x speedup over prior methods. Then, we describe methods to vectorize each HDC block. Implementation on a vector accelerator achieves a 12.2 x speedup and 7.1 x reduction in energy/prediction. Finally, we gain an additional 20% improvement in energy efficiency by finding the optimal balance between vector lanes and execution time, overall demonstrating the significant speed and energy improvements that a vector processor can provide for HDC.

Process technology scaling and hardware architecture specialization have vastly increased the need for chip design space exploration, while optimizing for power, performance, and area. Hammer is an open-source, reusable physical design (PD) flow generator that reduces design effort and increases portability by enforcing a separation among design-, tool-, and process technology-specific concerns with a modular software architecture. In this work, we outline Hammer's structure and highlight recent extensions that support both physical chip designers and hardware architects evaluating the merit and feasibility of their proposed designs. This is accomplished through the integration of more tools and process technologies---some open-source---and the designer-driven development of flow step generators. An evaluation of chip designs in process technologies ranging from 130nm down to 12nm across a series of RISC-V-based chips shows how Hammer-generated flows are reusable and enable efficient optimization for diverse applications.

DNN accelerators are often developed and evaluated in isolation without considering the cross-stack, system-level effects in real-world environments. This makes it difficult to appreciate the impact of Systemon-Chip (SoC) resource contention, OS overheads, and programming-stack inefficiencies on overall performance/energy-efficiency. To address this challenge, we present Gemmini, an open-source, full-stack DNN accelerator generator. Gemmini generates a wide design-space of efficient ASIC accelerators from a flexible architectural template, together with flexible programming stacks and full SoCs with shared resources that capture system-level effects. Gemmini-generated accelerators have also been fabricated, delivering up to three orders-of-magnitude speedups over high-performance CPUs on various DNN benchmarks.

This paper describes a scalable, highly portable, and power-efficient generator for massive multiple-input multiple-output (MIMO) uplink baseband processing. This generator is written in Chisel, and produces hardware instances for the distributed processing in a scalable massive MIMO system. The generator is parameterized in both the MIMO system and hardware datapath elements. The performance of several generator instances with different parameter values are validated by emulation on a field-programmable gate array (FPGA), demonstrating both functionality and scalability, and operation up to 6.4Gb/s data throughput.

Continued improvement in computing efficiency requires functional specialization of hardware designs. We present an agile design flow for custom SoCs using the Chipyard framework, an integrated SoC research and implementation environment for custom systems. Chipyard includes configurable, composable, open-source, generator-based designs that can be used across multiple stages of the hardware development flow while maintaining design intent and integration consistency. Through cloud FPGA simulation and rapid ASIC implementation, we demonstrate an iterative agile hardware design cycle which enables continuous validation of physically-realizable customized systems.