Determining a channel’s characteristics is a fundamental step for designing a high-speed link system. By identifying the properties of the channel, designers can gain insights into how to transmit a signal with low distortion and optimize a transceiver’s architecture. As the channel’s characteristics can be identified by analyzing its single-bit pulse response (PR), obtaining an accurate PR plot is critical for reliable channel characterization. Therefore, it is preferred to measure the PR in situ to minimize the parasitic effects. In this work, we introduce a novel approach for measuring PR in situ, designed to quickly and accurately generate undistorted plot results. To prove the efficacy of the proposed method, we designed an on-chip sampling scope circuit and fabricated a test chip in 28-nm CMOS technology. While being able to measure a distortion-free PR, the proposed method demonstrates a more than$10^{5}$times faster pulse acquisition rate than prior arts.

This paper presents compact single-ended wireline transceivers with software-generated receiver front-ends. The developed software framework significantly shortens the physical design time of 1/N-rate wireline receiver front-ends. The physical layouts of various receiver front-ends were software-generated in four different CMOS technology nodes (28 nm, 40 nm, 65 nm, and 90 nm) with four different front-end architectures targeting various data rates. In the post-layout simulation, the receiver front-ends generated within a second by the software achieved nearly the same performances as the manually-designed receiver front-ends that require more than about 30 hours of design time. For demonstration, we generated 8 Gb/s full-rate, 10 Gb/s half-rate, 12 Gb/s, and 20 Gb/s quarter-rate receiver front-ends, and fabricated them with a manually-designed feed-forward equalization transmitter in 28 nm CMOS process. The transceivers were measured with the data rate up to 20 Gb/s while consuming 1.39 pJ/b at the channel loss of −9.2 dB. The transceiver with software-generated receiver achieved the highest data rate per area as well as the smallest area among the relevant prior arts while reducing the physical design time of the receiver front-end by more than 140,000 times.

This paper presents a compact single-ended inverter-based transceiver with swing improvement for short-reach links. The low output impedance of the transmitter enlarges the output swing and the eye size to overcome large single-ended noise while relaxed impedance matching provides good signal integrity. For good area efficiency, the proposed transmitter utilizes an inverter driver which is much smaller than the conventional source-series termination driver and thus occupies only$42.5 ~\mu \text{m}^{2}$. By taking the advantage of a large signal swing, the receiver consists of only four slicers and latches to minimize area overhead and to simplify the design. The transceiver was fabricated in 28-nm CMOS technology and tested at supply voltage of 1.13 V. The transmitter achieved a large output swing of 850 mV, which is 50.4 % larger than the conventional source-series termination transmitter. At the far-end of a channel consisting of a 1 m SMA cable and a 17 mm printed circuit board trace, the transmitter achieved eye openings of 440 mV and 234 mV at 16 Gb/s (−2.7 dB) and 20 Gb/s (−8 dB), respectively. Even with a large switching noise of 100 mV, thein-situeye at the receiver was measured 114 mV with 7.4 dB loss.