Logic Built in Self Test (LBIST) has been a key technology for on-chip and in-field testing, enabling quick go/no-go verification. LBIST technology uses Pseudo-Random Pattern Generators (PRPGs) to apply patterns to the scan chain elements to target random pattern testable faults. The pseudo random data appears as random 0’s/1’s in the scan chains but is predictable based on the starting PRPG value or seed. This approach helps detect a good number of faults but comes at the cost of high scan switching. The input pseudo-random scan data can contain over 25% switching during the scan loading operation. This combined with 25% on the output or unload side, at times can result in a 50% scan switching. Unless planned for during implementation, this high amount of scan switching can introduce power issues within the design causing inconsistent failures. Some solutions for this include shutting off complete channels or setting up some custom PRPG logic, but this minimizes the pseudo-randomness of the scan input data. With some scan chains disabled, failures that require a mix of 0/1’s on those scan bits can never be tested. In this paper, we present new PRPG gating concepts that can help control the input scan switching activity but still allow scan chains to get pseudo-random 0/1’s during scan load operations. This allows for predictable Low Power pseudo random scan input data and can reduce scan switching to as low as 10% in LBIST modes.

Scan based diagnosis is an industry proven approach to aid in identifying the root-cause of defects in silicon. ATPG fault models such as stuck-at, transition are typically used for identifying the best possible fault location(s) that explain the potential reason for tester failures. With lower technology nodes, the correlation between behavior of defects in silicon and the modeled faults is quickly declining. Opens and Shorts either internal to library cells or the cell interconnects, timing defects at a specific location or on a specific path are some examples. With the addition of these new defect types, newer and complex fault models have to be considered for diagnosis. Each of these fault models will add substantial run time overhead to diagnosis making the yield analysis process longer. This paper proposes a new approach to perform diagnosis with all the newer fault models in a tractable time. Proposed approach allows simpler addition of newer fault models with marginal run time overhead. Experimental results indicate up to 2.97X run time reduction with proposed approach.

Test time is directly proportional to cost of test. Reducing test time of each integrated circuit (IC) increases profitability. During silicon bring-up and yield analysis of complex ICs, such as those used in artificial intelligence (AI) and automotive applications, debug and diagnosis are crucial components. Debugging scan chain defects in compression modes is a complex problem and typically requires additional one-hot patterns. Applying these patterns not only increases the cycle counts substantially but also enforces a cumbersome two-pass flow typically run outside a production flow. This paper discusses a production scan pattern generation algorithm for designs with test compression that reduces scan channel load and unload times, among other savings, thereby reducing costs of testing. Results on industrial designs show cycle count reduction of up to 80X over one-hot scan patterns without loss of test coverage and diagnosability.

Automotive designs demand the highest possible test coverage for safety and reliability. One approach is to add as many test points as possible to the circuit. To avoid increasing the die size, test point sharing can be used to maximize the number of test point nodes while using fewer test point flops. While test point sharing reduces area overhead, extra wiring is needed leading to congestion which again limits the number of test points that can be added. This paper presents a method to reduce wiring congestion when sharing a large number of test points. Our method also reduces the impact sharing can have on fault coverage. Test point sharing is optimized in the physical implementation tool to reduce wiring and congestion leading to improvements in PPA. Results from five automotive designs show up to a 67% reduction in wiring for test point logic, an average 24% reduction in congestion, and improvements in PPA. Alternatively, one can increase the number of test points and achieve a 1.62% improvement in LBIST coverage without introducing additional congestion or impacting PPA.

Logic diagnosis attempts to identify defects within a microprocessor using only a logical model of the design with no knowledge of the physical layout. Physically aware logic diagnostics greatly improves callout resolution, enabling diagnosis of new fault types, but presents scalability issues for large, complex processor designs. This paper highlights solutions needed to create an efficient high-volume physical diagnosis pipeline. Results of the proposed system are demonstrated on 7nm processor designs.

With the advanced technology used in the semiconductor manufacture process, systematic defects related to layout patterns and litho process are the major cause of yield issues. In this industry session, we invite three experts from three EDA companies to share their experiences of diagnosis and yield learning.

The main goal of existing scan chain diagnosis approaches is to identify a point (or range of points) in the scan chain(s) at which values are directly corrupted due to a defect. A common assumption made in these techniques is the defect causing failure is in the scan chain/path itself. Based on the real silicon failure analysis over years, this assumption is often found to be correct, but not always. Specifically, in cases where a single defect is expected (stress fails and field returns), yet multiple chains fail, this assumption is more often incorrect. In these cases, the defect was found to be in the clock and control signal logic. This paper proposes an improved approach to diagnose defects on clock and control signal lines to enhance accuracy of scan chain diagnosis. Experimental results on injected clock and control signal defects demonstrate the effectiveness of the proposed technique. Physical Failure Analysis (PFA) on selected silicon devices confirmed the results of proposed technique.

Recent innovations in Test Compression are enabling implementation of very high compression ratios. This paper analyzes the impact of high compression on resolution and performance of conventional diagnosis methods. The diagnosis resolution is observed to be unaffected by increasing the compression ratio if there are sufficient failures and patterns. However, the diagnosis run times increase significantly, resulting in significant throughput issues in Layout-aware Volume Diagnosis. A new diagnosis approach is proposed for high compression modes that achieves best possible resolution with significant run time speedup. Experiments on large industrial designs show up to 4.7X speedup with no loss of diagnosis resolution.

Volume Diagnosis is a proven methodology to significantly improve the yield enhancement rates. One of the key factors of success to this methodology is being able to perform diagnosis on hundreds to thousands of failing dies using a limited amount of computational resource in a tractable time. This paper presents a new Multiple Device Diagnosis (MDD) system to significantly improve the throughput of volume diagnosis by performing logic diagnosis on a group of failing devices. Experiments conducted on large industrial designs with randomly selected groups of failing devices demonstrated up to 12X increase in speed-up with the proposed system.