Hybrid memory systems composed of Non-volatile memory (NVM) and DRAM to exploit the high density of NVM and low access latency of DRAM. Phase Change Memory (PCM), a type of non-volatile memory, is a viable choice for main memory. High write latency and high voltage requirements for PCM lead to Biased Temperature Instability (BTI) aging and performance degradation. De-stressing the memory circuit at regular intervals controls BTI aging. Memory performance can be enhanced by migrating the highest write count memory pages across memory units. Migration and de-stress halt the service of regular requests and affect the performance of the system. Therefore, it is crucial to control migration and de-stress to enhance hybrid memory performance while mitigating BTI aging. We propose DOPMig, a de-stress-aware page migration technique. The policy migrates write-intensive pages to DRAM at regular intervals but opportunistically parallel to the de-stress operation. This method of background migration helps to reduce the migration overheads and improves performance. DOPMig achieves a performance gain of 22%, and improves memory service rate by 15%, and increases DRAM access by 24%.

Hybrid memory composed of DRAM and PCM exploits benefit of both types of memory. The random page placement in such memories may cause write-intensive pages to be placed in PCM partition, which may adversely affect the memory performance due to the higher write latency of PCM. Migration of write-intensive pages to DRAM helps in improving memory service time. Existing techniques migrate pages having write access count greater than a predefined threshold. These techniques do not examine the access pattern once the choice to migrate the page has been made. This might lead to unnecessary migrations because the page may have been hot before the decision, but the number of access may have dropped after migration. To accurately identify the hot page, we propose an access-based prudent page migration method which uses an eDRAM buffer to migrate hot pages from PCM to DRAM. In this paper, we present a look-before-you-leap migration technique where after a page is identified as a hot page, makes a thoughtful decision regarding whether to migrate or not to migrate it.

A memory controller manages the flow of data to and from attached memory devices. The order in which a set of contending memory requests from different tasks are serviced significantly influences the rate of progress and completion times of these tasks. This in turn may affect the Quality-of-Service (QoS) delivered by these tasks. In this article, we focus towards the design of a QoS-aware memory controller targeted towards soft real-time systems. The proposed memory controller tries to generate an urgency-based schedule for the contending memory requests based on the allowable response time latencies associated with each request. The objective is to improve task-level response time predictability while maximizing acquired QoS. Exhaustive experiments carried out using real memory traces and standard simulation tools exhibit the practical efficacy of the proposed memory controller design.

Hybrid memory systems with a combination of DRAM and Non-Volatile Memory (NVM) types can make use of scalability and performance of both NVM and DRAM. Random placement of pages in Phase Change Memory (PCM) with more write accesses incurs higher write latencies. So, migrating write intensive pages from PCM to DRAM helps to reduce execution time and memory response time for applications. Existing techniques mainly focus on selecting the page migration candidate and migrate it immediately when it becomes eligible. This direct migration approach can hamper the response time of regular memory accesses. So, in our paper, we identify migration candidates and in addition, schedule when they can be migrated to DRAM. To realize this, we have used Selection and Run-time Scheduling of page Migration (SRS-Mig), a frame-based scheduling approach for migrations and read/write requests. SRS-Mig reduces migration overhead and guarantees future accesses to migrated pages to yield an improved execution time and memory response time for the applications. Experimental evaluation shows 30% improvement in execution time; 26% improvement memory response time, and considerable energy savings with the existing baseline techniques.

Phase Change Memory (PCM) has emerged as a viable alternative to traditional DRAM memories especially in real-time embedded systems, due to their higher density and lower leakage power dissipation. However, PCM comes with its own drawbacks. Although, the performances of DRAM and PCM are comparable for memory reads, PCM is about three times slower in terms of write latency, and suffers from significantly lower write endurance. The high write latency of PCM may be detrimental to delivered QoS and may lead to deadline misses in real-time systems. To circumvent the problem, this paper proposes a novel memory scheduling scheme which employs separate write request buffer in order to prioritize reads over writes. The read requests are scheduled using an urgency based scheduler where urgency depends on allowable response times of tasks. The write requests are serviced when there are no pending reads using a similar urgency based scheduler as used for read requests. Experimental evaluation using standard benchmarks reveal that the proposed scheme is able to achieve better normalized QoS compared to existing scheduling techniques for PCM and comparable access latencies with respect to DRAM.