To effectively transmit data to and from satellites requires a complex and robust RF communication system. Using adaptive link techniques, several different types of signal modulations may be used to maximize satellite efficiency depending on a variety of unexpected channel impairments. We propose an FPGA based neural network system capable of learning these RF signal modulations using a supervised learning technique designed for low power, high-efficiency in-orbit deployment. Thus, as signal modulation changes, a receiving satellite would be able to recognize this modulation update without adjustment from an operator, or any delay due to control signal transmission.Due to the limited resources of FPGAs, we implement CNN transfer learning on the FPGA instead of full CNN training. The work presented demonstrates a convolutional neural network (CNN) capable of learning and recognizing a set of modulation schemes commonly used to transmit RF information. We are capable of recognizing the modulation scheme from the I and Q data channels directly, with no preprocessing or data conversion required other than segmenting the incoming signal into a set of uniform normalized samples. We perform a network design and size analysis, showing that we can obtain reasonably high accuracy using networks with a relatively low number of trainable parameters. Thus, modulation recognition can be performed through rapid feedforward computation. Given that a user of this system may wish to receive a signal using a modulation scheme that the network has not previously learned, we demonstrate that transfer learning can learn new modulation schemes by retraining only the fully connected layers in the CNN. Thus, this type of network would excel in outer space deployment using high-efficiency transfer learning hardware. Our FPGA system utilized 2.1W power and processed 219 data samples per second for training. This made it about 59x more energy efficient than a desktop GPU for the same task.

There is increasing demand for specialized hardware for training deep neural networks (DNNs), both in edge/IoT environments and in high-performance computing systems. The design space of such hardware is very large due to the wide range of processing architectures, DNN configurations, and dataflow options. This makes developing DNN processors quite complex, especially for training. We present TRIM, an infrastructure to help hardware architects explore the design space of DNN accelerators for both inference and training in the early design stages. The model evaluates at the whole network level, considering both interlayer and intralayer activities. Given applications, essential hardware specifications, and a design goal, TRIM can quickly explore different hardware design options, select the optimal dataflow and guide new hardware architecture design. We validated TRIM with FPGA-based implementation of DNN accelerators and ASIC-based architectures. We also show how to use TRIM to explore the design space through several case studies. TRIM is a powerful tool to help architects evaluate different hardware choices to develop efficient inference and training architecture design. Experimental results show that TRIM is a powerful tool for rapidly exploring the design space of DNN architectures for training and inference.

Compact online learning architectures can be used to enhance internet of things devices, allowing them to learn directly on received data instead of sending data to a remote server for learning. This saves communication energy and enhances privacy and security, as the data is not shared. This paper presents a 3D memristor based multicore architecture capable of on-line learning, where a mixed signal design utilizes memristor crossbars to both store synaptic weights and to carry out analog dot product computations. A 3D memristor architecture is one where several memristor crossbars are stacked vertically on top of each other to reduce the area footprint of a chip. A variety of deep learning applications can be processed using the proposed architecture, and we show how the simulated architecture is able to learn and classify several datasets. In this work we also examine how changing the number of vertically stacked crossbars within a neural core impacts energy, time, and area requirements of the architecture.

Specialized ultra-low power deep learning architectures with on-chip training capability can be useful in variety of applications that require adaptability. This paper presents such a processor design, Socrates-D 2.0, a multicore architecture for deep neural network based training and inference. The architecture consists of a set of processing cores, each with internal memories to store synaptic weights. Additionally, we present a method to map traditional deep learning networks to our multicore architecture and show that there is minimal impact in training accuracy. The system level area and power benefits of the specialized architecture are compared with the earlier generation of Socrates-D. Our experimental evaluations show that the proposed architecture can provide 1.25× area and 1.19× energy efficiency than the previous version of Socrates-D.