In the world of IoT and embedded systems, security depends on reliable cryptographic circuits like Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) to verify devices and keep data secure. While these components are usually implemented separately, recent approaches suggest combining them can save space and increase efficiency. This paper introduces a unified design for both a TRNG and a PUF, using the same entropy source: the gate-tunneling currents found in CMOS transistors. By drawing on manufacturing imperfections, this approach creates both unique device identifiers and high-quality random bitstreams for secure operations. Through measurements and validation using the NIST SP 800-22 tests, we show that the design meets stringent randomness requirements. This integrated solution could provide a practical, efficient answer for security in resource-limited systems.

This paper presents a novel ISFET architecture with in-pixel ADC for large-scale integration and on-chip computational capabilities. Each pixel is composed by a comparator connected to a set of memory elements, storing in-pixel each conversion. Using this sensing scheme, the entire frame of ISFET pixels is acquired and stored in one single ADC cycle, eliminating the need for global or column-level ADCs and making this architecture scalable to larger arrays without instrumentation overhead. To enable compensation of ISFET non-idealities such as trapped charge, a novel gate-bootstrapping mechanism is introduced, enhancing the ADC dynamic range without additional circuitry and accommodating a trapped charge compensation range of 4.45 V. Fabricated in standard 180nm CMOS technology, the system is composed by a 16x16 ISFET array, a global DAC and a Digital Control Unit that enables operation and off-chip communication. The entire frame is acquired in 51.2 μs with a pixel power consumption of 10.15 μW, while storing the result in-pixel and eliminating the need for off-chip memories.

In order to normalise measured concentrations of biomarkers in sweat, many of which are sweat rate dependent, a multi-modal analysis which measures flow rate alongside biomarker concentration is required. This paper presents an overview of current methods, as well as a detailed design of a calorimetric system to measure the flow rate of sweat, including the fluidic channel, signal conditioning circuits, and power regulation. Through simulation of the full system using LTSpice and SOLIDWORKS FlowSimulation, the final design achieved a minimum resolution of 0.85 pL/min, as well as an average error of 1.87% across the 0.5 to 20 pL/min measurement range.