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Chenyang Kong

dblp:212/7157 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 77% Electronic design automation · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › analog and mixed-signal circuits › oscillator design
voltage-controlled oscillator design
0.412020
A Synthesizable Constant Tuning Gain Technique for Wideband LC-VCO Design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › analog circuit design automation
analog circuit optimization
0.112020
A Synthesizable Constant Tuning Gain Technique for Wideband LC-VCO Design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020

Methods — techniques the papers use, named apart from their topics

iterative optimization · 0.4capacitor array weighting · 0.4
YearPublicationVenuePosition
2020 A Synthesizable Constant Tuning Gain Technique for Wideband LC-VCO Design
abstract
In this paper, an iterative method is proposed for the optimization of wideband voltage-controlled oscillators (VCOs). The proposed method attempts to improve two significant performance metrics of wideband VCOs, i.e., the nonuniform band distribution and the nonconstant tuning gain KVCO. To address these nonideality issues, we introduce the deviation as a prior knowledge for calibration in each iteration step. The optimal capacitor array weighting plan can be asymptotically approached through multiple iterations. To demonstrate the efficacy of the proposed method, we use it to implement a 1-to-2.4-GHz LC-VCO and achieve a frequency tuning range of 82.4%. The optimized LC-tank involves 64 mixed cells, and each cell contains 2-bit binary-weighted switching capacitors, leading to 256 tuning bands. The LC-VCO with the synthesized tank achieves uniform frequency steps around 5 MHz with the relative error within ±4.4%. Meanwhile, the tuning gain KVCO is around 10 MHz/V with the relative error within ±3.2%. For this LC-VCO design, each iteration step costs about 55.9 s. After seven iterations, we approach the convergent solution where both the relative errors of the frequency steps and the tuning gains satisfy the given specifications.
Xiaoxue Sun, Chenyang Kong, Jun Tao 0001, Zhangwen Tang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2