The wafer-on-wafer (WoW) stacked structure exhibits pioneering advantages in near-memory computing but encounters challenges in 3D analysis due to the miniaturization of vertical connection structures and the simplification of vertical drivers. This article introduces a 3D unified analysis method (3D-UAM), which facilitates standard-cell-level signal integrity (SI) analysis across the 3D WoW stacked structure with hybrid processes, including a comprehensive 3D vertical connection theoretical model that bridges the dynamic random access memory (DRAM) and logic netlists. The accuracy of the 3D-UAM is confirmed through consistency analysis with the results of the 3D field model. The authenticity of the 3D-UAM is validated through correlation analysis with the physical test results from the WoW stacked DRAM test chip. The practicality of the 3D-UAM is demonstrated through channel optimization on a 20-layer DRAM WoW structure and power integrity (PI) analysis for the WoW stacked structure.

DRAM latency has remained almost constant over decades and has become a performance bottleneck of computing systems. In this study, we propose a low-cost DRAM architecture enabling dynamic reconfiguring of row decoder to provide reduced latency with high flexibility and reliability. We apply minimum changes to row decoders and allow dynamic reconfiguration to switch array blocks between two modes: 1) normal mode, where the DRAM array behaves in the same manner as the conventional DRAM does and 2) low latency mode, where two DRAM cells in the neighbor array blocks are coupled to operate as a logical cell and reduce latency reliably according to the differential principle. On the basis of an industrial open bitline (BL) cell array, we only change the word-line decoding scheme but keep the cell array and sense amplifiers (SAs) untouched to avoid modifications to the DRAM process for cost and reliability considerations. Our circuit simulation shows that the low-latency mode can reduce row-to-column delay and row access strobe time by 25.7% and 23.2%, respectively. We evaluate the reduced-latency LPDDR4 DRAM on various workloads. Compared with the JEDEC standard DRAM, our proposal provides a maximum system performance improvement of 8.5%. We believe that our proposal is a reliable and cost-friendly solution to DRAM latency reduction.