Demo Data from EDBT 2026 / reviewers in the wild / expert
Krishnan S. Rengarajan
dblp:213/2322
· DBLP profile ↗
2ranked-venue papers
1as first author
1since 2021 · last 2025
0000-0001-5967-3005ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 87% Integrated circuit design · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
circuit simulation |
0.4 | 1 | 2020 | A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Electronic design automation › circuit simulation
mixed-signal simulation |
0.4 | 1 | 2020 | A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Integrated circuit design › semiconductor devices
silicon-on-insulator |
0.1 | 1 | 2020 | A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Methods — techniques the papers use, named apart from their topics
newton-raphson iteration · 0.4interpolation · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | A 9.62 mW LMV Cell for mm-Wave ApplicationsabstractIn this paper, we present an integrated current-reuse low-noise amplifier (LNA), mixer, and voltage-controlled oscillator (VCO) (LMV) as a single-stage RF front-end receiver for mm-Wave applications. Instead of using a basic cross-coupled oscillator FET configuration, the LMV cell now incorporates parallel gate-coupled oscillator FETs to enable its operation at mm-Wave frequencies. Furthermore, power optimization is achieved through adjustments to the mixer supply and oscillator bias tuning. This novel modification helps to achieve a lower power consumption and parasitic load on the LC tank circuit. The load is a low-pass operational amplifier in feedback configuration, which outputs a low intermediate frequency (IF) with a conversion gain of 43.5 dB. The presented LMV topology is realized in 40 LP bulk CMOS process and is operating at 34.62 GHz with a power consumption of 9.62 mW. Krishnan S. Rengarajan, Pulkit Kathuria, Soumya Rank, Sourav Nandi, Saroj Mondal |
ISCAS | 1 |
| 2020 | A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid PrototypingabstractIn this paper, a new look-up table (LUT) method is proposed to reduce the simulation time and the run time memory requirement for large logic and mixed signal simulations. In the proposed method, for the first time, circuit with multiple devices is replaced by one LUT model, called circuit LUT. The replacement results in significant reduction of the run time memory requirement. The replacement also reduces the number of interpolation steps to be performed at every Newton-Raphson iteration during the simulation that results in significant reduction of simulation time. With the proposed method, the simulation speed is improved by two times over the conventional LUT models developed for devices. In addition, 25% reduction in the run time memory requirement is also achieved by the proposed method. Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengarajan, Subramanian S. Iyer, Maryam Shojaei Baghini |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 5 |