As the integration level of integrated circuits continues to increase and the feature size of nanoscale chips continues to shrink, the possibility of triple-node-upsets (TNUs) occurring in circuits increases significantly. This paper proposes a latch, namely CLTNUSL, which offers stable resilience against TNUs in radiative environments while achieving a good balance between reliability and overhead. Unlike the conventional latches consisting of multi-input C-elements, the proposed CLTNUSL latch mainly consists of 16 interlocked dual-input inverters. Due to the small number of transistors, CLTNUSL achieves low area overhead. Due to the use of high-speed paths and clock gating techniques, CLTNUSL achieves low latency and low power consumption. Simulation results demonstrate CLTNUSL’s full recovery from TNU in all scenarios. Compared with the conventional TNU-hardened latch, CLTNUSL achieves minimal latency, power consumption, area overhead, and the delay-power-area product (DPAP). CLTNUSL reduces delay by 13.22%, power by 52.74%, area by 40.90%, and DPAP by 71.44% on average, compared with state-of-the-art latches. Process-Voltage-Temperature (PVT) and Monte Carlo simulation results show that the CLTNUSL latch is less sensitive to temperature, voltage and process variations compared with conventional TNU self-recovery latches.

Electromigration-induced hillocks and voids in Cu interconnects pose increasingly significant reliability challenges to microelectronic devices, as device scaling and current density continue to rise in advanced integrated circuits. These defects can cause critical short-circuit and open-circuit failures. However, the quantitative mechanisms governing these failure modes remain insufficiently understood, limiting the precise prediction of defect morphology and growth dynamics. In this work, we develop a physically based phase field model to investigate the formation and evolution of hillocks and voids in Cu interconnects under electric current stressing, incorporating the influence of grain morphology. Our results show that hillocks tend to form and grow on the anode side, with directional mass migration inducing voids on the cathode side, leading to increased electrical resistance and potential signal degradation. Interconnects with finer polycrystalline structures exhibit more rapid hillock and void growth, due to the increased number of grain boundaries that enhance atomic diffusion pathways. Hydrostatic stress not only flattens void morphology but also accelerates the growth of both hillocks and voids. The stress-driven diffusion flux flows into the hillock regions adjacent to the anode, promoting the formation of taller hillocks. The proposed model qualitatively reproduces key features observed in experimental studies, offering microstructure-aware insights into electromigration-induced failure mechanisms and providing a foundation for predictive reliability analysis and design optimization of Cu interconnects.

Privacy-Preserving Mutual Authentication (PPMA) protocols utilize Physical Unclonable Function (PUF) and True Random Number Generator (TRNG) as security primitives to protect privacy. To ensure the security of Internet of Things (IoT) nodes in untrusted environments, PPMA keys and encrypted data must reside on the same chip. The concept of integrating PUF and TRNG on a single device has thus emerged as a new security paradigm. This paper proposes a novel lightweight, portable, multi-mode reconfigurable integrated PUF-TRNG architecture resistant to machine learning attacks. Through co-design, the architecture achieves the integration and switching among three modes: Arbiter Physical Unclonable Function (APUF), Ring Oscillator Physical Unclonable Function (RO PUF), and TRNG. The APUF mode leverages the RO PUF mode for assistance, endowing it with machine learning resistance, where the highest prediction rates using Logistic Regression (LR), Support Vector Machine (SVM), CMA (Comparative Model Analysis), and Deep Neural Network (DNN) algorithms are only around 60%. Additionally, a lightweight authentication protocol is proposed to further enhance resistance against machine learning attacks. In TRNG mode, the architecture has two outputs, each capable of generating random numbers at 800 Mbps, resulting in a total throughput of 1600 Mbps. The generated random numbers have successfully passed various tests, including NIST SP800-22, NIST SP800-90B, AIS-31, and TESTU01. In the NIST SP800-22 test, the pass rates for both outputs of the Artix-7 and Kintex-7 FPGAs are approximately 99%.

True random number generator (TRNG) is a key component in ensuring hardware security, and with the development of technologies such as high-speed communications, there is a higher demand for its generation rate. In this work, an ultra-high throughput rate TRNG based on a scalable cascaded full feedback ring oscillator (CFFRO) as the entropy source circuit is presented and implemented on Xilinx Artix-7, Kintex-7, and zynq UltraScale+ FPGAs devices. Unlike previous works, the proposed CFFRO is designed to be constructed as multiple parallel internal ROs, which, in turn, are sequentially cascaded and coupled to each other to disrupt the frequency spectrum of each ring oscillator and enhance the output uncertainty. Each internal ring oscillator in CFFRO can be used as an output for random numbers, creating multi-channel TRNG with parallel outputs and single-channel TRNG with multi-bit serial outputs. Measurements of the sequences extracted by both random number output schemes of TRNG show good randomness in the NIST SP800-22 suits and high entropy values in both the NIST SP 800-90B and AIS-31 testing suits, and the Dieharder suite verified the robustness under voltage and temperature variations. Moreover, due to the good extensibility of CFFRO, TRNGs with 2–8 channel counts are implemented in this work. At a sampling frequency of 400 MHz, the random sequences generated by 2–8 channel TRNGs can pass the tests.

This paper proposes a novel Agile Physical Compiler (APCer) for multi-port register files based on a standard cell library. It employs a Performance, Power and Area (PPA)-driven genetic algorithm to facilitate agile iterations and design generation. APCer can automatically iterate, generate, and optimize floorplan, rapidly creating efficient register file circuits and layouts with specified capacity and port numbers. Additionally, APCer responds to user-defined PPA requirements, enabling targeted design optimizations. It accelerates the register file design duration by over 40× and 20× compared with the full custom approach and existing compilers, respectively. Compared to existing compilers, APCer improves performance by 20.7% and reduces power consumption by 33.9%. Compared to the full custom approach, APCer improves performance by 31.5% and reduces power consumption by 28.8%.

This article proposes a novel and effective 14-transistors (14T) reconfigurable radiation-hardened static-random access-memory cell design under the SMIC 65-nm process, featuring a unique memory reconfigurability architecture with two operation modes, namely the high reliability (HR) mode and the triple-time memory (TTM) mode for meeting different radiation environmental requirements. The proposed HR mode provides strong protection of the memory arrays in harsh radiation environments. Compared with the traditional triple modular redundancy (TMR) structure, the proposed HR mode reduces area overhead by 30%, delay by 37%, and power consumption by 16%. The TTM mode uses the enable (EN) circuit to expand the capacity threefold in less harsh radiation environments, avoiding the area wastage caused by the traditional TMR structure. By implementing the two innovative operation modes, the proposed design overcomes the limitations of the traditional TMR structure, reducing area overhead while retaining the radiation hardening capability. In addition, this article presents a mode-switching mechanism composed of a detection circuit and an EN circuit. The detection circuit can detect errors in the reconfigurable architecture. With the proposed mode-switching mechanism, two operation modes can switch in response to different radiation environments. Besides, to ensure the normal operations of the TTM mode in radiation environments, the proposed 14T cell serves as a bitcell in the memory reconfigurable architecture. Compared with typical existing designs, such as radiation-hardened based design, writability enhanced, and dual interlocked storage cell (DICE) cells, the proposed 14T cell design has better delay, critical charge, and higher hold static noise margin.

With the advancement of semiconductor technology, circuits have become increasingly susceptible to errors induced by radiation. Traditional approaches to enhancing the resilience of circuits against single-node upsets (SNUs) are insufficient to meet the robustness standards of modern designs. This article proposes a high-performance, low-power latch, named high-performance low-power double-node upset resilient latch (HLDRL), which is designed to exhibit exceptional resilience against double-node upsets (DNUs). Its design has six intricately interconnected C-elements (CEs) and two three-input CEs, for error interception, ensuring robust performance even in the case of DNUs. The Technology Computer Aided Design (TCAD) tool is used to validate the effectiveness of the HLDRL. Besides, comprehensive simulations are conducted utilizing the advanced SMIC 55-nm process technology. These simulation results show that our proposed HLDRL latch can autonomously recover from any DNU and thereby ensure the integrity of the system. Moreover, compared with existing DNU-resilient latches, the proposed HLDRL latch exhibits substantial improvements in terms of multiple metrics. On average, the proposed latch achieves an impressive 29.39% dynamic power saving, a remarkable 40.04% increase in speed, a notable 4.81% reduction in area, and a substantial 53.96% decrease in the power-delay–area product (PDAP). In the post-layout simulation, the proposed latch achieves a 30.39% dynamic power saving, a 36.47% increase in speed, and an impressive 52.38% decrease in PDAP. Furthermore, the proposed latch demonstrates enhanced resilience against variations in process, supply voltage, and temperature (PVT).

As a core component in the field of information security, the true random number generator (TRNG) produces high-entropy random numbers by extracting unpredictable noise from the physical environment, exhibiting nonreproducibility and resistance to prediction. To address the challenges posed by interference in high-speed systems, maintaining stable throughput and entropy sources for TRNG, this article proposes an optimized TRNG that utilizes chaotic interference to refresh the cellular automata (IRCA) iterative algorithm. The IRCA-TRNG utilizes a self-timed ring oscillator (STR) and jitter to perturb the operation of chaotic cellular automata (CA) cells, achieving a high-throughput TRNG. The generated random sequences have successfully passed NIST SP800-22, TESTU01, NIST SP800-90B, and AIS-31 tests. A throughput of 1040 Mb/s has been achieved on Xilinx Artix-7 and PYNQ-K2 series development boards. Compared with the state-of-the-art works, the proposed TRNG demonstrates significant advantages in resource utilization and performance quality factors.

Low-energy, radiation-hardened chips play a crucial role in the application of aerospace electronic equipment. This is because aerospace chips are susceptible to soft errors caused by single event upsets (SEUs) from space particle bombardment, as well as impacts on energy efficiency. As a vital core component of chips, memory storage, its key nodes becoming more sensitive to technological advancement. Moreover, the limited energy supply of the anti-radiation chip and excessive power consumption can result in an excessive burden on the thermal control system. In this paper, a low-energy-enhanced critical charge 16TSRAM (SAW16T) is proposed. To demonstrate the relative performance of SAW16T, the state of art technologies of other radiation-hardened memory cells, such as SARP12T, RH12T, RSP14T, EDP12T, SIS10T and SUR16T, are compared. Simulations are conducted at 27 °C using a 65-nm CMOS technology with a supply voltage of 1.2V. All sensitive nodes of SAW16T are able to recover to their initial states after being affected by soft errors. The critical charge of node Q hits 300fc under typical (tt), slow (ss), and slow-N fast-P (snfp) process corners, whereas node S1's critical charge reaches 300fc in tt, fast (ff), ss, fast-N slow-P (fnsp), and snfp process corners, tripling the reference value in literature. SAW16T exhibits the shortest write access time compared to the aforementioned cells, with hold power consumption reduced by 99.9%, 49.95%, 43.8%, 21.6%, and 62.9%, compared to RH12T, RSP14T, EDP12T, SIS10T, SUR16T, respectively. Furthermore, SAW16T has been demonstrated superior performance in comprehensive performance evaluations.

As technology scales down, the critical charge (QC) of vulnerable nodes decreases, making SRAM cells more susceptible to soft errors in the aerospace industry. This article proposes a Soft-Error-Aware 16T (S8P8N) SRAM cell for aerospace applications to address this issue. The properties of S8P8N are evaluated and compared with 6T, DICE, QUCCE12T, WEQUATRO, RHBD10T, RHBD12T, S4P8N, SEA14T, and SRRD12T. Simulation results indicate that all vulnerable nodes and key node pairs of the proposed cell can recover to their original states when affected by a soft error. Additionally, it can recover from key multinode upsets. The write speed of the proposed cell is found to be reduced by 20.3%, 50.1%, 74.1%, 63.7%, and 50.41% compared to 6T, DICE, QUCCE12T, WEQUATRO, and RHBD10T, respectively. The read speed of the proposed cell is found to be reduced by 56.6%, 52.2%, 62.5%, and 35.2% compared to 6T, SRRD12T, RHBD12T, and S4P8N, respectively. It also shows that the hold power of the proposed cell is found to be reduced by 14.1%, 13.8%, 17.7%, and 23.4% compared to DICE, WEQUATRO, RHBD10T, and RHBD12T. Furthermore, the read static noise margin (RSNM) of the proposed cell is found to be enhanced by 157%, 67%, and 32% compared to RHBD12T, SEA14T, and SRRD12T. All these improvements are achieved with a slight area penalty.

Abstract The great demand for mobile blockchain computing power is often unsatisfied by terminal devices, so computational tasks are offloaded to edge computing servers. This paper proposes a new mobile communication blockchain assumption, forms a computing power alliance (CPA), and builds a smart contract‐based security model. First, mining difficulty compensates for the personal computing power outside the CPA to increase the block generation difficulty. Second, contract account funds are used to increase the cost of malicious nodes seeking to launch forking attacks, and the duration is used to limit mining. Finally, a court trial is opened to select validators to verify the fork. The auction algorithm is used to allocate computing power in the CPA, and a price utility function is constructed to maximize social welfare. The joint optimization algorithm increases the transaction price and improves the system security. Simulation results verify that the system security increases with the blocked funds and duration, and the forking attack success rate approaches zero as the number of validators increases. The proposed algorithm provides considerable sum utility and average revenue gains versus traditional methods under different numbers of mobile users and computational capabilities, and the security of the algorithm is also higher.

There are two primary defects in the existing UAV avoidance systems: the system is memoryless; airborne radars are used to detect long‐distance barriers, which are unreliable and expensive. The paper adopts the deep learning algorithm and ADS‐B communication system based on a satellite base station to solve the above problems. It divides the avoidance problem into two parts: short‐distance obstacle avoidance and long‐distance route planning. On the one hand, the system establishes the knowledge base storing the previous avoidance experience and the matching mechanism, realizing the correspondence between input and experience through a deep learning algorithm. They can dramatically improve the reaction speed and safety of UAVs. On the other hand, the system realizes the interconnection between UAV and the satellite base station through the ADS‐B communication system to replace the radars, putting the task of route planning on the satellite platform. Therefore, the satellite can achieve large‐scale and all‐weather detection to improve the overall safety of UAVs depending on its high and long‐range characteristics. The paper also illustrates the design elements of the RF baseband integrated ADS‐B transceiver and the simulation performance of the short‐distance avoidance system in the end, whose results show that the system can be applied to dense obstacle environments and significantly improve the security of UAVs in a complex domain.