Cellular network control procedures (e.g., mobility, idle-active transition to conserve energy) directly influence data plane behavior, impacting user-experienced delay. Recognizing this control-data plane interdependence, L25GC re-architects the 5G Core (5GC) network, and its processing, to reduce latency of control plane operations and their impact on the data plane. Exploiting shared memory, L25GC eliminates message serialization and HTTP processing overheads, while being 3GPP-standards compliant. We improve data plane processing by factoring the functions to avoid control-data plane interference, and using scalable, flow-level packet classifiers for forwarding-rule lookups. Utilizing buffers at the 5GC, L25GC implements paging, and an intelligent handover scheme avoiding 3GPP's hairpin routing, and data loss caused by limited buffering at 5G base stations, reduces delay and unnecessary message processing. L25GC's integrated failure resiliency transparently recovers from failures of 5GC software network functions and hardware much faster than 3GPP's reattach recovery procedure. L25GC is built based on free5GC, an open-source kernel-based 5GC implementation. L25GC reduces event completion time by ~50% for several control plane events and improves data packet latency (due to improved control plane communication) by ~2×, during paging and handover events, compared to free5GC. L25GC's design is general, although current implementation supports a limited number of user sessions.

With modern FPGAs' reconfiguration flexibility and abundant resources, FPGA-based test equipment has become a promising solution for low to mid-end test and measurement applications. However, FPGA structure and specifications limit the choice of tester architecture and achievable performance. In this paper, we design and implement an FPGA-based multi-channel data/timing formatter, a key component in automatic test equipment. The proposed formatter (1) adopts the EG (edge generator) pool concept to improve hardware utilization, (2) employs accuracy-driven EG scheduling to improve edge placement accuracy, (3) embeds a delay monitor for temperature compensation, and (4) allows inter-channel skew adjustment. A prototype five-channel formatter is implemented on Xilinx Spartan-6 FPGA. The per channel symbol rate is 100 Msps and the edge placement resolution is 200 ps.