MOTIVATION: Long-read phasing has been used for reconstructing diploid genomes, improving variant calling and resolving microbial strains in metagenomics. However, the phasing blocks of existing methods are broken by large Structural Variations (SVs), and the efficiency is unsatisfactory for population-scale phasing. RESULTS: This article presents a novel algorithm, LongPhase, which can simultaneously phase single nucleotide polymorphisms (SNPs) and SVs of a human genome in 10-20 min, 10× faster than the state-of-the-art WhatsHap, HapCUT2 and Margin. In particular, co-phasing SNPs and SVs produces much larger haplotype blocks (N50 = 25 Mbp) than those of existing methods (N50 = 10-15 Mbp). We show that LongPhase combined with Nanopore ultra-long reads is a cost-effective and highly contiguous solution, which can produce between one and 26 blocks per chromosome arm without the need for additional trios, chromosome-conformation and strand-seq data. AVAILABILITYAND IMPLEMENTATION: LongPhase is freely available at https://github.com/twolinin/LongPhase/. SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.

By analyzing the fault behaviors of conventional flash memory fault models, two new concise fault types are proposed: the 1-safe fault and the 0-safe fault. For a 1(0)-safe fault, if logic 1(0) is programmed into the faulty cell, the effect of the fault can be masked. Data shaping (DS) and the page address remapping (PAR) techniques are used to increase the masking probability. DS manipulates the data patterns so that they can be written into the flash pages safely. PAR scrambles the logical-to-physical address mapping for data words and buffer words. Since the effect of a fault is masked for a large proportion of faulty cells, the burden on the error-correction code (ECC) is reduced, as is the number of incorporated redundancies. A novel test-and-repair flow is proposed that uses DS and PAR and corresponding hardware architectures are also developed. A simulator is used to evaluate the hardware overhead, the repair rate, the yield, and the reliability. The experimental results show that these measures are significantly improved with an almost negligible hardware overhead.

Based on the fault behaviors of conventional fault models, the 1-safe and 0-safe fault types are derived in this paper. We can try to store the safe value of a flash cell such that the fault effects can be masked. To boost the masking probability, both the data inversion (DI) and the page address remapping (PAR) techniques are also proposed. DI tries to complement the data bits to be programmed if their values derivate from the safe values of the corresponding faulty flash cells. PAR manipulates the logical-to-physical mapping of data words and the buffer words such that faulty cells can be programmed with their safe values. Since most of the fault effects are masked, we can reduce the strength of the adopted ECC or the amount of incorporated redundancies. The corresponding hardware architectures are also developed. A simulator is developed to evaluate the hardware overhead, repair rate, and reliability. According to experimental results, these measures can be improved significantly with negligible hardware overhead.