This paper presents the design of an ultra-low power relaxation oscillator for Internet-of-Things (IoT) power management applications. The new design employs a dual-comparator architecture with a novel dynamic biasing technique to minimize power consumption. The biasing of both comparators is dynamically regulated to ensure their operation only during decision-making events, substantially reducing power consumption. The proposed oscillator achieves a power consumption of only 74.6nW at a stable frequency of 1.2kHz, exhibiting a standard deviation of merely 74Hz. The new design demonstrates a 73% reduction in power compared to the conventional design. The circuit is simulated in a 65nm, 1.2V CMOS process, with all results verified by post-layout simulation.

This paper presents the design and implementation of a miniaturized, low-noise Magnetic Tunnel Junction (MTJ)-based proximity sensor with a high-performance readout channel. The MTJ-based proximity sensor consists of 1102 circular pillars of 100um diameter arranged in series, providing accurate detection of subtle interactions, such as a finger approaching the sensor. The system exhibits a 54 dB gain and a bandwidth of 1 kHz, with a noise power density of less than 30 nV/√Hz at 100 Hz, ensuring high precision. The proximity sensor demonstrated linear behavior for distances from 18 mm to 45 mm, with a sensitivity sufficient to detect low magnetic field variations. Experimental validation of the sensor shows a high degree of accuracy (R2= 0.9715), confirming its potential for use in touchless control, mobile technology, and industrial applications.

This paper presents a novel approach to reservoir computing (RC) using Granular Vortex-Based Magnetic Tunnel Junctions (GV-MTJs) for temporal applications. GV-MTJs, with their unique magnetic domain configurations and granular structures, provide the necessary fading memory and non-linear dynamics essential for RC. The vortex core’s oscillatory motion within the device allows for temporal correlation of inputs, giving fading memory, while grain-induced non-linear resistance and frequency variations enhance data dimensionality. Our findings indicate that varying device parameters can affect the relaxation time and gyrotropic frequency in both simulation and experiments. Relaxation times range from 100-140 ns and frequencies from 250-100 MHz. Through experiments, the classification error was reduced by 27% for the best sample, others showed limited potential. Due to signal application speed constraints, the fading memory is not fully utilized. However, the inherent RC capabilities of GV-MTJs are validated. This paper highlights the promise of GV-MTJs in neuromorphic computing and suggests avenues for future research to optimise their use in practical applications.

This article presents a low-power fully CMOS temperature sensor in a 65 nm process, suitable for monitoring the battery-powered application-specific integrated circuit (ASIC) designs. The circuit converts a proportional-to-absolute-temperature (PTAT) current to a complementary-to-absolute-temperature (CTAT) binary code using a low-power time-to-digital converter to-digital converter (TDC). To enhance conversion efficiency, we introduce a two-stage dynamic comparator that consumes 40% less power than conventional designs by enabling the preamplifier only when precise detection of the integration stop time is required. The 0.16$\text{mm}^{2}$prototype consumes only 0.97 nJ/conversion, achieving a resolution figure of merit (FoM) of 0.018 nJ$\cdot $$\text{K}^{2}$. Measurements show an inaccuracy of$\pm 0.85~^{\circ }$C ($3\sigma $) over a temperature range of –$20~^{\circ }$C to$+ 120~^{\circ }$C.

This paper presents a chopper-stabilized three-stage operational amplifier (OpAmp) with a unity gain bandwidth of 69 MHz and an input referred noise density of 3 nV$/\surd{Hz}$. The proposed design achieves a stable unity gain by proposing a new pole and zero scheme with very low power consumption, drawing only 3.3 mA from a 1.8 V power supply while driving a load capacitor as large as 100pF. To achieve rail-to-rail input swing, the design uses both NMOS and PMOS differential pairs at the input and biases them in the subthreshold region to provide an identical net trans-conductance over the rail-to-rail input common mode. Furthermore, an adaptive biasing is employed and the current sources are kept ON during large signal transitions at the input, thus eliminating crossover distortion and providing a high slew rate of 40 V/$\mu$s at a 100 pF load capacitor. The design employs chopping at 2.5 MHz and is enhanced with a local ripple reduction loop, making the OpAmp suitable for high gain and wide bandwidth applications with less filtering required. The design also reduces the input bias current significantly from 500 nA to 1.5 nA by buffering the input and applying it to the modified bootstrap switches. The proposed OpAmp, fabricated in a 0.18$\mu$m CMOS process, exhibits a maximum offset of 4.5$\mu$V, a flicker noise corner frequency of 246 Hz, a DC gain of 146 dB, a power supply rejection ratio of 123 dB, and a common mode rejection ratio of 116 dB.

Many classification applications rely on real-time processing and detection of RF signals at high frequencies. RF signal sampling requires sophisticated hardware, i.e., broadband analog front-ends and high-speed analog-to-digital converters according to the well-known Shannon-Nyquist theorem. Such devices either are expensive or suffer from limited detection bandwidths and sampling rates. Here, we proposed a novel spintronic-based classification front-end for real-time analysis and classification of RF signals. In comparison to the conventional CMOS-based systems, the proposed system can increase the classification speed dramatically while consuming an order of magnitude less power.

Spiking neural networks (SNNs) are envisioned to be a better alternative to artificial neural networks (ANNs) for targeted applications. Multi-core implementation of SNNs has been built to achieve a resource-efficient design. However, managing the spike traffic congestion while routing the spikes between different cores requires a performance-resource tradeoff to avoid any packet loss. This paper presents a novel router architecture servicing ongoing packets in a 2-D mesh network while guaranteeing no packet drop. Here, the packets are distributed across different paths to reduce spike traffic. The proposed router suitable for a$16\times 16$network occupies an area of 0.001mm2 in 28nm CMOS technology, while consuming 75 fJ/transmission.