EDBT 2026 Demo / reviewers in the wild / expert
Gopabandhu Hota
dblp:213/7636
· DBLP profile ↗
5ranked-venue papers
2as first author
4since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-author · 4 since 2021Artificial intelligence and machine learning · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Clo-HDnn: Continual On-Device Learning Accelerator with Hyperdimensional Computing via Progressive SearchabstractClo-HDnn is an on-device learning (ODL) accelerator designed for emerging continual learning (CL) tasks. Clo-HDnn integrates hyperdimensional computing (HDC) along with low-cost Kronecker HD Encoder and weight clustering feature extraction (WCFE) to optimize accuracy and efficiency. Clo-HDnn adopts gradient-free CL to efficiently update and store the learned knowledge in the form of class hypervectors. Its dual-mode operation enables bypassing costly feature ex- traction for simpler datasets, while progressive search reduces complexity by up to $61 \%$ by encoding and comparing only partial query hypervectors. Achieving 4.66 TFLOPS/W (FE) and 3.78 TOPS/W (classifier), Clo-HDnn delivers $7.77 \times$ and $4.85 \times$ higher energy efficiency compared to SOTA ODL accelerators. Chang Eun Song, Keming Fan, Soumil Jain, Gopabandhu Hota, Haichao Yang, Leo Liu, Meng-Fan Chang, Carlos H. Diaz, Gert Cauwenberghs, Tajana Rosing, Mingu Kang |
HCS | 5 |
| 2024 | Bio-plausible Learning-on-Chip with Selector-less Memristive CrossbarsabstractOne of the practical realizations of large-scale neuromorphic systems requires an area-efficient memristive crossbar array as a key building block supporting high-density synaptic connectivity. Conventional memristor-based AI accelerators rely on selector transistors to reduce sneak path-induced cross-talks, although other means can be equally effective. Removing the selector element on each memristor cross-point significantly improves array density (down to 4F2) and lowers power consumption. We present an integrated reconfigurable neuromorphic platform interfacing a selector-less 16x16 RRAM memristor crossbar array with peripheral row and column instrumentation for robust learning and inference with applications to AI on the edge. Bio-plausible local Hebbian-like incremental outer-product learning rules are mapped onto direct implementation across the memristive crossbar array, updated in a sequence of partial outer-product combinations presented at the periphery of the array. Our system provides a user-configurable platform to accommodate a broad spectrum of emerging non-volatile memory device technologies for synaptic crossbar arrays with embedded adaptive functionality for general AI and cognitive neuromorphic computing. Jeong-Hoon Kim, Soumil Jain, Gopabandhu Hota, Jaeseoung Park, Duygu Kuzum, Gert Cauwenberghs |
ISCAS | 3 |
| 2023 | A Versatile and Efficient Neuromorphic Platform for Compute-in-Memory with Selector-less Memristive CrossbarsabstractMemristive crossbar arrays have become essential building blocks in the realization of large-scale neuromorphic systems with high-density synaptic connectivity. Traditionally, memristor-based accelerators are equipped with selector elements to reduce cross-talk through sneak paths along unselected lines. However, due to the large drive strength required for selector elements, it comes at the cost of synaptic crossbar density. Selector- less alternatives require careful design of crossbar peripheral circuits to mitigate or eliminate sneak path-induced cross-talk. We propose a hybrid integrated platform that interfaces a selector- less memristor crossbar array with peripheral row and column instrumentation for array-parallel programming and readout for AI learning and inference applications. The proposed switched-capacitor voltage-sensing instrumentation avoids the need for current-sensing schemes with voltage-clamped sense lines that are typically used to mitigate the sneak path issues in selector- less crossbars but are substantially less energy-efficient than voltage-sensing. Our board-level platform is implemented using commercial off-the-shelf (COTS) data converters and switched capacitors, and is controlled by a Xilinx Spartan-6 FPGA. The system offers programmable sense times to characterize memristors over a wide range of resistances and the capability to switch between a transient-domain measurement and steady-state measurement to offer the desired trade-off between accuracy and energy efficiency during inference parallel readout. We implement a differential weight-encoding scheme to improve the accuracy of matrix-vector multiplication. The system also supports an array-level programming scheme for parallel write access as well as online learning-in-memory for neuromorphic applications through outer-product incremental decomposition of the weight matrix. Thus, our system offers a generic, user-configurable, and versatile platform to support wide dynamic range measurements of synaptic crossbar arrays and cognitive neuromorphic computing with emerging non-volatile memory devices. Soumil Jain, Gopabandhu Hota, Sangheon Oh, Jiajia Wu 0008, Preston Fowler, Duygu Kuzum, Gert Cauwenberghs |
ISCAS | 2 |
| 2022 | Hierarchical Multicast Network-On-Chip for Scalable Reconfigurable Neuromorphic SystemsabstractState-of-the-art neuromorphic computing architectures to date suffer from interconnect scalability required for large-scale neural processing. We present a high-performance and low-overhead multicast network-on-chip (NoC) architecture for hierarchical address event routing (Multicast-HiAER) suitable for large-scale reconfigurable neuromorphic systems. Each building block of this efficient NoC architecture consists of several multi-cast advanced high-performance buses (mAHB) running in parallel for high-bandwidth inter-core spike event transmission. This architecture for scalable event routing can help to implement brain-scale sparse neural network connectivity distributed across neuromorphic processing cores, with network constraints typical of locally dense and globally sparse neuron connectivity. For a demonstration using a Xilinx Virtex Ultrascale VU37p FPGA, we have shown an $8\times 8$ grid of mAHBs running at 512MHz clock performing Level-1 and Leve1-2 inter-core communication at top bandwidth of 420M events per second per 128k neuron node in the hierarchy. This peak absolute bandwidth supports spike event registration with sub-ms latencies under worst-case conditions of all postsynaptic destinations being off-core. Gopabandhu Hota, Nishant Mysore, Stephen R. Deiss, Bruno U. Pedroni, Gert Cauwenberghs |
ISCAS | 1 |
| 2019 | An Adaptive Anaphylaxis Detection and Emergency Response SystemabstractAllergic Reactions can range from mild rashes to severe conditions, sometimes even leading to anaphylaxis and sudden death. Lack of sufficient prior patient data and a need of physician's immediate supervision calls for a solution which can be deployed at large to prevent the sudden death occurring due to anaphylactic shocks and further collect data to enable fast detection in future situations. This paper describes an integrated ecosystem comprising of several on-body patient devices connected to a central server with a doctor at one of the client nodes. An on-body device consists of physiological signal acquiring sensors, abnormality detector, and smart-phone for uploading the anomalous data to a server for further classification. Gathering anomalous data from the patients, the cloud processes them through a binary adversarial classifier based on physician's annotation of anaphylaxis occurrence. The adversarial classifier has been incorporated to tackle data insufficiency because of its faster convergence. Gopabandhu Hota, Abhilash Nandy, Kshitiz Goel, Dishank Yadav, Saumo Pal, Ankush Roy |
CBMS | 1 |