It's been one year since Richard Goering told us that the EDA RTL-to-GDSII world was about to change. What have we learned? Who's winning, and who's not? This panel, consisting of the leading large and upcoming players in this space, will deliver concrete data to differentiate leading approaches to achieving design closure. Does the solution lie in raw speed and RTL optimization, with the synthesis-place-route back end just a commodity? Does the solution lie in new metrics for design convergence, and symmetric multiprocessing platforms for efficiency? Does the solution lie in a holistic, unified architecture of data model and tools? Or does the solution lie in extensions and unifications of existing production-proven logic, timing, and layout optimization technologies? A hard-hitting panel session will reveal the answers!