EDBT 2026 Demo / reviewers in the wild / expert
N. Sandeep
dblp:214/6288
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3ranked-venue papers
0as first author
3since 2021 · last 2025
0000-0002-2670-2049ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Switched-Capacitor-Based DC-AC Boosting Circuit: Synthesis and OperationabstractThe novel inverter topologies are often intriguing and ignite interest in knowing the rationale behind their circuit synthesis, which is usually not detailed. This article provides a step-by-step topological derivation of a novel common ground (CG) multilevel inverter with an aim to motivates researchers for proposing new attractive topologies applicable to emerging fields. Further, this article proposes a dual-output, nine-level boosting inverter that combines CG and common-positive (CP) features. By integrating the CGCP characteristics, the proposed inverter draws a non-zero continuous input current (unlike the traditional CG or CP-based inverter), making it highly suitable for photovoltaic (PV) systems. With the CGCP feature, the proposed inverter eliminates ground leakage current caused by PV parasitic capacitance. In addition, the usage of switched-capacitors (SCs) inherently boosts the input voltage. Further, the SCs are self-voltage balanced without relying on a dedicated sensor circuit, reducing the control complexity. Unlike the conventional dual port CG inverters, the proposed CG and CP inverters are fault-tolerant as an independent unit and in combination as well. The decoupled output ports feed the loads independently of each other, thus, can also feed unequal loads. A detailed comparative study is presented to highlight the figures of merit of the proposed inverter against the well-established topologies. Finally, the feasibility of the proposed inverter is validated through several experimental tests conducted on a 1 kW laboratory prototype, and the results are presented. Anil Jakhar, N. Sandeep |
IEEE Trans. Circuits Syst. I Regul. Pap. | 2 |
| 2025 | An Improved Dual-Output Five-Level Buck PFC Rectifier With Reduced Switch CountabstractResearch on power converters featuring multipurpose capabilities holds a lot of potential in power electronics. This paper presents an AC/DC converter with a reduced component count and dual DC output terminals. The semiconductor devices in the proposed topology undergo reduced switching (ON/OFF) transitions in a switching cycle, considerably lowering the switching losses. Furthermore, the multicarrier pulse width modulation control architecture allows for the simultaneous feeding of single and double equal/unequal loads without sacrificing converter stability. Additionally, because of its continuous current mode functioning, fewer capacitive and inductive filters are needed at the input and output sides. Experimental verification has been done on the proposed transformerless multilevel rectifier topology in steady-state and dynamic operating conditions. Finally, a detailed comparative assessment is included to demonstrate the superior performance of the proposed topology. Ankush Koli, N. Sandeep, Harpal Tiwari |
IEEE Trans. Circuits Syst. I Regul. Pap. | 2 |
| 2023 | Switched-Capacitor Based Bridgeless Totem-Pole PFC Converter for EV ApplicationsabstractThis paper presents a hybrid totem-pole (TTPL) PFC AC-DC converter that utilises a switched-capacitor (SC) cell for electric vehicle (EV) charging applications. The converter has the capability to function as a component of an OBC system, specifically for LV battery charging. It is suitable as a front-end converter for ratings up to 3.3 kW. Conventional boost PFCs exhibit a restricted ability to deliver a lower DC output than the input AC magnitude. The use of an additional stage to obtain lower DC outputs results in an increased number of components, decreased efficiency, and lower power density. The addition of an SC-cell with the highly efficient TTPL PFC configuration is used to address the issue of obtaining low output. A comprehensive analysis of the operational modes, accompanied by a detailed exposition of the design methodology, is presented. A 1 k W prototype of the converter design has been simulated and developed. The results indicate that the converter can function within a broad input voltage range of 90–270$V$AC and maintain an input current THD that falls within the limits specified by IEC61000-3-2. G. K. Naveen Kumar, Arun Kumar Verma, N. Sandeep |
IECON | 3 |