In this work we propose a fully differential amplifier, designed in 22 nm FDSOI (fully depleted silicon on insulator), with supply voltage of 0.8 V and achieving 8 GHz gain bandwidth (GBW), 80 dB dc gain and phase margin of 49 degrees in unity gain configuration with a load capacitor of 2 pF. The two-stage folded cascode gain boosted transconductance amplifier (OTA) has been designed to have a inter-stage gain of 8 in a high speed analog-to-digital converter (ADC) and is verified by post-layout simulations.

Compute-In-Memory (CIM) enables accelerating multiply-accumulate computations (MACs) by non von Neumann architecture analog crossbars. However, computation precision and power efficiency suffer from parasitic wire resistance and power-consuming data-converters with conventional voltage-mode crossbar. Increasing crossbar size to further enhance computation/power efficiency can only be achieved on the premise that those problems can be solved. This work proposes a charge-transfer-based crossbar, where the accumulation is performed by counting the transferred charges into capacitors. Thanks to the time-discrete property of the charge transfer and adaptive body-biasing (ABB) current generator, the entire proposed crossbar is almost fully dynamic and very insensitive to parasitic wire resistance without DAC/ADC needed. In addition, adaptive reference technique is applied to realize a self-adjustable operating range for quantitated neural network computations. The proposed crossbar prototype is designed with 22nm-FDSOI and post-simulated with a size of $128 \times 128$. A computation and power efficiency of 1024GOP/s and 78TOPS/w is achieved for computation with 4-bit inputs, 1-bit weight, and 4-bit output. Both computation-and power efficiency can be further enhanced by enlarging the crossbars’ size without any significant loss of the computation precision.

The size of crossbar-like resistive multiplication accumulation (MAC) accelerators is restricted by parasitic interconnect resistances limiting the computation efficiency. In order to understand the impact of the interconnect (wire) resistance on the computation accuracy, this work proposes a modelling methodology for adapting the neural network weights regarding the weight error caused by wire resistance. Even more, this work investigates the maximal achievable crossbar size based on the proposed design variable "the minimal allowed weight error ratio Ron/Reqv" instead of using an iterative numerical method. Using the proposed method this work investigate the computation accuracy improvement through splitting the layer computation into multiple small crossbars. The result indicates that simply separating the computation into multiple small crossbar does not improve the accuracy always. Considering the minimal Ron/Reqv can more easily result in a proper crossbar size.