This work explores the use of asynchronous approximate multiply-accumulate (MAC) operators and research ways to alleviate the inherent area overhead of such circuits, while leveraging on asynchronous circuits advantages. It analyzes three approximate MAC architectures with varying error rates and area trade-offs. Accurate and approximate, synchronous and asynchronous MAC operators are compared. Experiments show it is feasible to decrease the area overhead of the accurate asynchronous MAC from 8.1$\times$ down to 1.6$\times$ by recurring to approximate multipliers, for varying controlled error rates. The use of asynchronous quasi-delay insensitive (QDI) circuits allows applying extensive voltage scaling to all asynchronous MAC operators. Power and energy per operation can thus be significantly reduced, achieving savings of up to 2.66$\times$ in power and 3.17$\times$ in energy per operation when compared to the accurate asynchronous MAC.

This paper explores asynchronous FIFOs design choices, more specifically FIFOs from the quasi-delay insensitive (QDI) template family. It proposes eight different asynchronous FIFO structures on a CMOS 45nm technology, using a QDI standard cell library. Structures are exercised through analog-mixed-signal simulation, ranging from nominal to subthreshold supply voltages. Follows a comparison of area, throughput and power efficiency. The experimental results allow inferring a technique for designers to select the most adequate QDI FIFO flavor for specific circuits. Insight on the experiments assesses the beneficial and/or limiting effects of using the specific cell library.

Internet of Things devices require innovative power efficient design techniques that ensure correct operation in harsh environments, where using synchronous design can be challenging. The timing sign-off of synchronous circuits requires analysis and optimisation under multiple corners and operating modes. Considering that energy efficient circuits demand dynamic voltage ranges and harsh environments impose significant variations, design sign-off may become prohibitively expensive. An alternative is quasi-delay-insensitive asynchronous design, which presents robustness against timing variations, simplifying timing sign-off. This paper leverages recent developments in asynchronous circuits design automation to achieve higher degrees of energy efficiency using voltage scaling, while ensuring solid robustness to variability.