This paper presents the Quantum-Inspired Error Detection Protocol (QIEDP), a novel error correction scheme for serial communication that adapts quantum stabilizer code principles—specifically multi-dimensional parity relationships and syndrome-based detection—to classical digital systems. QIEDP implements a$(15,7,5)$linear code providing 2-bit error correction with$O(1)$computational complexity using pre-computed lookup tables containing 105 correctable error patterns. Simulation results demonstrate consistent Bit Error Rate (BER) improvements of 1.6-1.8× over conventional UART with parity in typical IoT operating conditions (9-15 dB Signal-to-Noise Ratio(SNR)), despite syndrome collisions limiting double-bit correction to 85.7% efficiency. The protocol achieves 46.7% code efficiency with 100% single-bit and 85.7% double-bit error correction rates using only 360 bytes of memory, making it particularly suitable for resourceconstrained IoT applications requiring reliable communication in electromagnetically noisy environments.

Modulo polynomial multiplication is an essential mathematical operation in the area of finite field arithmetic. Polynomial functions can be represented as tensors, which can be utilized as basic building blocks for various lattice-based post-quantum cryptography schemes. This paper presents a tensor-based novel modulo multiplication method for multivariate polynomials over$GF(2^{m})$and is realized on the hardware platform (FPGA). The proposed method consumes$6.5\times$less power and achieves more than$6\times$speedup compared to other contemporary single variable polynomial multiplication implementations. Our method is embarrassingly parallel and easily scalable for multivariate polynomials. Polynomial functions of nine variables, where each variable is of degree 128, are tested with the proposed multiplier, and its corresponding area, power, and power-delay-area product (PDAP) are presented. The computational complexity of single variable and multivariate polynomial multiplications are$O(n)$and$O(np)$, respectively, where$n$is the maximum degree of a polynomial having$p$variables. Due to its high speed, low latency, and scalability, the proposed modulo multiplier can be used in a wide range of applications.

Lattice-based homomorphic encryption schemes provide strong resistance against quantum and classical computer-based adversary security attacks. In this article, we present a software-hardware co-design of two partially homomorphic encryption (PHE) schemes employing an ARM-System on Chip (ARM-SoC) and an field programmable gate array (FPGA). This provides necessary acceleration to PHE methods in the ecosystem mentioned above. The first PHE scheme is designed for generic homomorphic encryption, while the second scheme is aimed at resource optimized lightweight IoT-driven applications. For seamless assimilation, a robust and reliable low latency data transfer protocol is developed between the FPGA-based accelerator IP and ARM-SoC host system. The proposed PHE schemes are realized using Verilog hardware description language on multiple FPGA platforms. The proposed lightweight scheme is$52.71\times$more resource-efficient than the pipelined BGV RLWE-based method. It exhibits$1.43\times$and$1.29\times$better throughput than non-pipelined and pipelined realizations of the BGV RLWE-based scheme. The proposed hardware accelerators realized on FPGA platforms having lesser clock speed and consuming lower resources showcase significant speedup compared to their software implementations making our proposed method an efficient alternative to enhance security in edge-enabled IoT devices.

Rapid evolution of E-world demands delay, power and area optimized digital circuits/systems while still meeting the security requirements of the cryptography applications. Cryptographic hash functions (which are considered the workhorse of security layers) provide compressive and non-invertible outputs. This signifies that approximate implementation of cryptographic hash functions can provide improvements in delay, power and area without considerable change in security level. In this paper, we first examine likelihood of infusing approximation in cryptographic hash functions and then propose a methodology to evaluate the effects of approximation. Further, we demonstrate four approximate pipelined implementations of Secure Hash Algorithm 1 (SHA-1). Our simulation results show that the proposed approximate pipelined SHA-1s provide significant improvements in delay, power and area with negligible change in security level.