Thermal issues of 3D-ICs have become increasingly severe in recent years. Thus, thermal simulation is needed to ensure thermal safety during the design stage. However, performing thermal simulation iteratively requires a significant amount of time. As a result, a fast and accurate method for thermal prediction is a promising alternative to improve the turnaround time. In this paper, we propose a fast thermal prediction method using machine learning models. In the training phase, we employ two models: one for the initial three time steps and another for the subsequent time steps. To enhance prediction accuracy, we introduce two types of features: spaced-windowed features and time-decayed features. These features help us to capture spatial and temporal information effectively. In our experiment, the mean absolute error for the predicted temperature is 1.12°C, and the maximum error is 7.27 °C. In the prediction phase, we achieve a 116X speed-up compared to a commercial tool. With our proposed method, users can predict transient thermal profiles quickly and accurately to ensure thermal safety.

This paper presents an integrated IR-Informed Timing and Timing-Aware IR Optimization flow with an IR-drop predictor. The proposed flow couples an IR-Informed Timing Optimizer with a Timing-Aware IR Optimizer to consider the mutual impact between IR-drop and timing during optimization. Then, we leverage a fast ML-based IR-drop predictor to quickly estimate the IR-drop after each iteration of optimization, which enables fast switching between the IR optimizer and timing optimizer. We further propose Feature Approximation to speed up the inference time of the IR-drop predictor. On two 7nm designs, the proposed flow closes timing and eliminates at least 90.6% of IR-drop violations. The Feature Approximation achieves 67% speed up in the runtime of the overall flow. Our optimization flow can be applied to a 945k-cell design with 7,578 IR-drop violations within 3 hours, demonstrating its practicality.

Thermal issues during testing of Very Large Scale Integration (VLSI) chips have become more severe as design complexity increases. Test frequency optimization is needed because high test frequencies can cause thermal damage to circuits under test (CUT), while low test frequencies can result in long test time. In this paper, we propose three techniques to minimize the test time of ATPG scan tests without peak temperature violation. First, we propose a single test frequency optimization using machine learning predicted power maps. Second, we partition a test schedule into subschedules and perform multiple test frequency optimization for each subschedule to further reduce test time. Third, we show that we can partition a test schedule by our proposed Power Gap to obtain an even shorter test time. Our experimental results show that the total test time at our optimized multiple test frequencies is 45.91% shorter than the total test time at the original single test frequency.

High test power causes thermal damage to chips under test. We need power and thermal analyses to ensure thermal safety of ATPG patterns. This requires long runtime and large disk storage because there are many cycles in ATPG patterns. In this paper, we propose power and thermal predictions for test applications. To save runtime, we use multiple ML models and decay surface models for power and thermal predictions, respectively. To save storage, we build features from flip-flop values, so we don't need internal logic values from gate-level simulation. Our mean absolute percentage error (MAPE) for power prediction is less than 8%. Our mean absolute error (MAE) for thermal prediction is less than 1.2°C. We enable transient thermal analysis of long ATPG patterns, with 75X runtime speedup and 118X storage reduction. Our predictions are scalable with test speed, so they can be used to optimize test time while ensuring thermal safety.

Vector-based dynamic IR-drop analysis of the entire vector set is infeasible due to long runtime. In this paper, we use machine learning to perform vector-based IR drop prediction for all logic cells in the circuit. We extract important features, such as toggle counts and arrival time, directly from the logic simulation waveform so that we can perform vector-based IR-drop prediction quickly. We also propose a feature engineering method, density map, to increase correlation by 0.1. Our method is scalable because the feature dimension is fixed (72), independent of design size and cell library. Our experiments show that the mean absolute error of the predictor is less than 3% of the nominal supply voltage. We achieve more than 495 speedups compared to a popular commercial tool. Our machine learning prediction can be used to identify IR-drop risky vectors from the entire test vector set, which is infeasible using traditional IR-drop analysis.

Manually analyzing the results generated by EDA tools to waive or fix any violations is a tedious, error-prone and time-consuming process. By automating these time-consuming rigorous manual procedures by aggregating key insights across different designs using continuing and prior simulation data, a design team can speed up the tape-out process, optimize resources and significantly minimize the risk of overlooking must fix violations that are prone to cause field failures. In this paper, a machine learning based generic waiver system is proposed which continuously learns to improve with new design data using K-means clustering and nearest neighbor algorithms for risk scoring. The system has been used on new designs to demonstrate on-chip Electromigration (EM) waiver (EMWaiver) mechanism that yielded highly confident results.