With the development of semiconductor technology nodes, the sizes of standard cells become smaller and the number of standard cells is dramatically increased to bring into more functionality in integrated circuits (ICs). However, the shrinking of standard cell sizes causes many problems of ICs such as timing, power, and electromigration (EM). To tackle these problems, a new style structural pre-route (SPR) is proposed. Such type of pre-route is composed of redundant parallel metals and vias so that the low resistance and the redundant sub-structures can improve timing and yield. But the large area overhead becomes the major problem of inserting such pre-routes all over a design. In this paper, we propose a machine learning-based approach to predict the insertability of SPRs for placed designs. In addition, we apply a pattern visualization method by using a guided backpropagation technique to see in depth of our model and identify the problematic layout features causing SPR insertion failures. The experimental results not only show the excellent performance of our model, but also show that avoiding generating the identified critical features during legalization can improve SPR insertability compared to a commercial SPR-aware placement tool.

2021 ICCAD CAD Contest Problem B is an extended problem from 2020 ICCAD CAD Contest Problem B [1]–[2] for addressing more complex constraints. In the physical implementation, the common approach is to divide the problem into the placement and routing stage. By doing this divide-and-conquer approach, it may cause conservative margin reservation and miscorrelation. In order to achieve multiple advanced objectives in terms of Power, timing Performance and Area, so called PPA, a certain amount of cell movement at the routing stage become a desired functionality in an EDA tool. 2021 ICCAD CAD Contest Problem B encourages the research in the techniques of routing with cell movement to achieve multiple objectives in the advanced process nodes (less than 7 nm). We provided (i) a set of benchmarks and (ii) an evaluation metric of multiple objectives including power factor, the criticality of timing critical nets, the maximum number of moving cells, and the total routing length optimization that facilitate contestants to develop and test their new algorithms.

With the continuous scaling down of process nodes, standard cells become much smaller and cell counts are dramatically increased. Pin accessibility becomes one of the major issues causing design rule violations (DRVs). To tackle this problem, many recent works apply machine-learning-based techniques to predict whether a local region has DRV or not by regarding global routing (GR) congestion and local pin density as the main features during the training process. Empirically, however, DRV occurrence is not necessary to be strongly correlated with the two features in advanced nodes. In this article, we propose the first work of deep-learning-based DRV prediction using pin pattern as our major feature to directly identify whether a DRV will exist or not due to bad pin accessibility of the given pin pattern. Unlike most of the existing models that can only be used for DRV prediction, the proposed models can be applied to guide detailed placement for pin accessibility optimization during physical design. Experimental results show that the proposed models are greatly superior than those of previous studies in terms of all quantitative metrics. Additionally, the numbers of DRVs can be dramatically reduced by applying the proposed model-guided detailed placement flow.

In physical implementation, the common approach is to divide it into the placement stage and the routing stage. By doing this divide-and-conquer approach, it may cause conservative margin reservation and mis-correlation. To address this problem, ICCAD-2020 contest encourages the research in the techniques of resolving this mentioned problem in the divide-and-conquer place & route approach. We provided (i) a set of benchmarks and (ii) an evaluation metric that facilitate contestants to develop and test their new algorithms.

In advanced semiconductor processes, the dramatic shrink of layout features has made a significant impact on circuit delay and electromigration (EM). Recently, meshed stack vias (MSVs) have been proposed as a solution to improve circuit timing and signal integrity, each of which is a multi-layer mesh structure composed of parallel metal shapes and vias. Due to the introduced MSV rules and more and more complicated design rules, MSV design becomes a very challenging problem, while no previous work has addressed this issue. In this paper, we propose the first work of MSV design by developing two different methods: an integer linear programming (ILP)-based and a dynamic programming (DP)-based methods. Unlike most previous works devoting themselves to formulating sophisticated constraints for each complicated design rule, we propose an automatic constraint generation (ACG) framework to iteratively resolve design rule violations (DRVs) without any effort in understanding all design rules, which contributes to a general MSV design methodology applicable to different technology nodes. Experimental results show that both the ILP-based and DP-based approaches can averagely achieve 92% MSV insertion rate for a set of industrial benchmarks. In addition, by adopting the proposed ACG framework, 100% MSV insertion rate can be achieved without causing any DRV.

With the development of advanced process nodes of semiconductor, the problem of pin access has become one of the major factors to impact the occurrences of design rule violations (DRVs) due to complex design rules and limited routing resource. Many state-of-the-art works address the problem of DRV prediction by adopting supervised machine learning approaches. However, those supervised learning approaches extract the labels of training data by generating a great number of routed designs in advance, giving rise to large effort on training data preparation. In addition, the pre-trained model could hardly predict unseen data and thus may not be applied to predict other designs containing cells that are not used in the training data. In this paper, we propose the first work of cell library-based pin accessibility prediction (PAP) by using active learning techniques. A given set of standard cell libraries is served as the only input for model training. Unlike most of existing studies that aim at design-specific training, we propose a library-based model which can be applied to all designs referencing to the same standard cell library set. Experimental results show that the proposed model can be applied to predict two different designs with different reference library sets. The number of remaining DRVs and M2 shorts of the designs optimized by the proposed model are also much fewer than those of design-specific models.

With the feature size shrinking down to 7 nm and beyond, the impact of wire resistance is significantly growing, and the circuit delay incurred by metal wires is noticeably raising. To address this issue, a new technique called via pillar insertion is developed. However, the poor success rate of the via pillar insertion process immediately becomes an important problem. In this paper, we explore the causes of via pillar insertion failures by experiments on the ISPD 2015 benchmarks, which are embedded with a real industrial cell library. The results show that the reasons for the low success rate may be due to track misalignment, power and ground stripe overlapping, and insufficient margin area. Therefore, we propose the first detailed placement flow which is aware of via pillars to maximize the success rate of via pillar insertion. In the proposed flow, we first filter out infeasible cell rows and then move the via pillar-inserting cells to their eligible positions. Next, we adopt a two-stage legalization method with high flexibility on cell ordering based on a dynamic programming-based detailed placement algorithm. Finally, we improve congested rows with a global moving process. Experiment results show that our algorithm improves the insertion rates by 54-58%, and achieves over 99% insertion rate on average.

Due to the rapid advance of integrated circuit (IC)-related technologies, design complexity is dramatically increasing in printed circuit boards (PCBs). Nowadays, a dense PCB contains thousands of pin shapes and signal nets, and such a huge net count makes the manual design of PCBs an extremely time-consuming task, especially in the routing phase. Bus routing, which consists of assigning all the buses to routing layers and topologically routing them on each layer while satisfying some constraints, is one of the most difficult steps in PCB routing. In addition, to take timing into consideration, all bits of a bus are highly preferred to have approximately the same length which are referred to as the length-matching issue. In advanced technology nodes, moreover, routing tracks are provided to help router adhere to design rules and help mask coloring. In this article, we develop a sophisticated bus router which optimizes routability, wirelength, as well as length-matching while simultaneously considering track resources, obstacles, and other design constraints. Experimental results show that the proposed algorithm flow can outperform the state-of-the-art bus routers in terms of the total routing cost and the min-max length difference for the benchmarks provided by the 2018 CAD contest at ICCAD.

With the continuous scaling down of process nodes, standard cells become much smaller and cell counts are dramatically increased. Pin accessibility becomes one of the major issues causing design rule violations (DRVs). To tackle this problem, many recent works apply machine learning-based techniques to predict whether a local region has DRV or not by regarding global routing (GR) congestion and local pin density as the main features during the training process. Empirically, however, DRV occurrence is not necessary to be strongly correlated with the two features in advanced nodes. In this paper, we propose the first work of deep learning-based DRV prediction using pin pattern as our major feature to directly identify whether a DRV will exist or not due to bad pin accessibility of the given pin pattern. Unlike most of existing models that can only be used for DRV prediction, the proposed models can be applied to guide detailed placement for pin accessibility optimization during physical design. Experimental results show that the proposed models are greatly superior than those of previous studies in terms of all quantitative metrics. Additionally, the numbers of DRVs can be dramatically reduced by applying the proposed model-guided detailed placement flow.

With the dramatic shrink of feature size and the advance of semiconductor technology nodes, numerous and complicated design rules need to be followed, and a chip design can only be taped-out after passing design rule check (DRC). The high design complexity seriously deteriorates design routability, which can be measured by the number of DRC violations after the detailed routing stage. In addition, a modern large-scaled design typically consists of many huge macros due to the wide use of intellectual properties (IPs). Empirically, the placement of these macros greatly determines routability, while there exists no effective cost metric to directly evaluate a macro placement because of the extremely high complexity and unpredictability of cell placement and routing. In this paper, we propose the first work of routability-driven macro placement with deep learning. A convolutional neural network (CNN)-based routability prediction model is proposed and embedded into a macro placer such that a good macro placement with minimized DRC violations can be derived through a simulated annealing (SA) optimization process. Experimental results show the accuracy of the predictor and the effectiveness of the macro placer.

In order to support the pad-limited application-specific integrated circuit (ASIC) designs, the flip chip package is used and provides the highest chip density compared to other packaging technologies. In this paper, we propose the first work of peripheral-input and -output (I/O) free-assignment flip-chip routing considering practical bump pad and I/O pad constraints and flexibilities. Unlike previous studies regarding all nets as the same, we differentiate signal and power/ground nets and set different bump pad assignment constraints for substrate layout optimization. In our flow, a global routing-based I/O-bump assignment algorithm is proposed with a multicommodity flow network model. Afterward, two detailed routing algorithms minimizing the total wirelength are presented. Finally, a dynamic programming (DP)-based I/O pad planning technique is applied to further reduce the number of wire bends. Experimental results based on modified industrial cases show that our algorithm flow not only achieves 100% routability of all testcases but also minimizes total wirelength, total wire bends, and bump utilization.

In order to support the pad-limited Application-Specific Integrated Circuit (ASIC) designs, the flip chip package is used and provides the highest chip density compared to other packaging technologies. In this paper, we propose the first work of free-assignment flip-chip routing considering practical bump/IO pad constraints and flexibilities. Unlike previous studies regarding all nets as the same, we differentiate signal and power/ground nets and set different bump pad assignment constraints for substrate layout optimization. In our flow, a global routing-based IO-bump assignment algorithm is proposed with a multi-commodity flow network model. After that, a detailed routing algorithm minimizing total wirelength is presented, which determines optimal relay points with a linear programming (LP) formulation. Finally, a dynamic programming (DP)-based IO pad planning technique is applied to further reduce the number of wire bends. Experimental results based on modified industrial cases show that our algorithm flow not only achieves 100% routability of all testcases but also minimizes total wirelength and bump utilization.

Mismatches caused by random and systematic variations among identical designed devices usually dominate the performance of analog circuits, where the former can be controlled by increasing area, while the latter should be tackled by careful layout design. Most of existing studies propose analog placement methodologies with the common centroid constraint to mitigate the linear systematic gradient effect. However, nonlinear gradient error compensation should also be addressed for circuits requiring high performance. This paper presents a current source placement algorithm considering quadratic (second order) gradient error for a high-accuracy current-steering digital-to-analog converter to pursue excellent linearity. A new switching scheme and a submatrix swapping technique are proposed to maximize quadratic gradient compensation, and a simulated annealing-based matrix perturbation algorithm is also proposed to directly minimize integral nonlinearity (INL). In addition, to tackle the extremely high complexity of current source interconnections, we model the routing instance as a branch assignment problem and propose an optimal greedy-based algorithm, which is inspired by the well-known left-edge algorithm. The experimental results show an order of magnitude reduction in INL compared to a state-of-the-art nonlinear gradient-aware current source placement approach and better dynamic performance in post-layout simulation.