We derive Singleton-type bounds on the free distance and column distances of trellis codes. Our results show that, at a given time instant, the maximum attainable column distance of trellis codes can exceed that of convolutional codes. Moreover, using expander graphs, we construct trellis codes over constant-size alphabets that achieve a rate-distance trade-off arbitrarily close to that of convolutional codes with a maximum distance profile. By comparison, all known constructions of convolutional codes with a maximum distance profile require working over alphabets whose size grows at least exponentially with the number of output symbols per time instant.

Massive MIMO is a pivotal technology for 5G and beyond, significantly enhancing spectrum efficiency and system capacity by deploying numerous receiving antennas at the base station. However, the increasing number of antennas imposes strong requirements for effective interference suppression in uplink MIMO detection. While traditional MMSE-IRC provides excellent performance in mitigating interference, its computational complexity scales cubically with the number of receiving antennas, limiting its practical applicability in massive MIMO systems. This paper presents a learning-based algorithm employing Mini-batch Gradient Descent (MBGD) to solve the weight matrix of MMSE-IRC, complemented by convergence acceleration strategies that incorporate adaptive initial learning rate determination and noise-plus-interference power regularization. Convergence and robustness of the proposed algorithm are validated across diverse modulation schemes, interference levels, and antenna configurations. Performance results indicate that, under high interference conditions, the iteration count of the proposed method is merely 12.5% that of traditional MBGD, while its BER performance exceeds that of conventional MMSE-IRC by approximately 0.5 dB, achieving a reduction in complexity from$O\left(N_{r x}^{3}\right)$to$O\left(N_{t x} N_{r x}\right)$.

Multiple Input Multiple Output (MIMO) is a critical component of modern wireless communication systems, widely utilized for its enhancement of system capacity. However, one of the major challenges of MIMO is the high complexity of the detection algorithm. In this paper, we propose a novel low-complexity detection algorithm based on multi-layer perception (MLP) and stochastic gradient descent (SGD). This algorithm significantly accelerates convergence using zero-forcing initialization and momentum optimization method. Additionally, a fixed-point optimized hardware architecture is proposed. The proposed design achieves up to 2.39× higher area efficiency with respect to the existing solutions, making it a promising candidate for practical application.

With the rapid development of the Internet of Things (IoT), device and data security has attracted huge academic attention in recent years since conventional security methods are barely feasible in IoT circumstances. Traditional encryption methods require extensive computation complexity, which requires several hardware resources and power consumption. Meanwhile, due to the low-power requirement, most IoT devices are lightweight with limited computing and storage capabilities. The dilemma leads to the need for a lightweight encryption method with decent data protection strength. Chaotic encryption can be applied in the IoT because of the characteristics of determinacy and strong randomness. However, its safety and hardware overhead are positively correlated with implementation precision. Therefore, this article performs a quantitative analysis of the system under different precision conditions. Then, a hybrid chaotic encryption scheme with dynamic precision is proposed, which balances power consumption and security protection level. Finally, the proposed design is implemented by Verilog and synthesized using SMIC 65-nm CMOS technology. The evaluation results proved that the proposed ASIC provides decent encryption strength under diverse precision, effectively overcoming the influence of limited precision with low-hardware resources and power consumption.

Hybrid low-density parity-check (LDPC) decoding combines conventional Belief-Propagation (BP) algorithm with stochastic decoding to achieve high performance and low complexity simultaneously. However, lossy and inefficient stochastic-to-binary (S2B) conversion brings extra performance degradation and decoding latency. In this paper, a bit-serial stochastic updating based hybrid decoding (BSSU-HD) is proposed, which employs fully correlated stochastic (FCS) check nodes (CNs) and probability tracers assisted variable nodes (VNs) to accomplish accurate and efficient S2B conversion. Two strategies, including random source selection and tracing speed switching, are proposed to further improve performance and convergence. A BSSU LDPC decoder for IEEE 802.3an is designed in a 65-nm CMOS process, which occupies 4.6 mm2 silicon area and achieves a throughput of 200.8 Gb/s at$E_{b}/N_{0} = 4.4$dB with 500 MHz clock frequency from a 1.2 V supply voltage. The power and energy efficiency are 2.933 W and 14.61 pJ/bit, respectively. To the best of our known, it achieves the best decoding performance, the highest throughput and hardware efficiency among state-of-the-art IEEE 802.3an LDPC decoders. We also verify that the BSSU-HD can achieve better performance for multi-rate 5th generation (5G) New Ratio (NR) LDPC codes than conventional algorithm, which greatly extends the application of the stochastic decoding.