Urmimala Chatterjee

dblp:215/1781 · DBLP profile ↗
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4ranked-venue papers
1as first author
3since 2021 · last 2025
0000-0002-8934-6774ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-author · 3 since 2021
YearPublicationVenuePosition
2025 On-Chip I/O ESD Protection for GaN-on-SOI Integrated Circuits
abstract
Gallium Nitride (GaN) platforms are reshaping the efficiency, frequency, and form factor of power electronics integrated circuits. However, the absence of p-channel transistors of GaN technologies makes traditional electrostatic discharge (ESD) protection for integrated circuits (ICs) ineffective. This letter proposes a protection network for input/output pins that leverages the unique conduction properties of enhancement-mode GaN transistors in the third quadrant of their current-voltage (I-V) plane. Experimental measurements confirm the viability of the proposed solution as a library element of the process design kit.
Katia Samperi, Urmimala Chatterjee, Salvatore Pennisi
ISCAS2
2025 Monolithically Integrated Bootstrapped Gate Driver With a 200-V GaN Power Switch
abstract
This paper presents the design and experimental measurement of a fully integrated gate driver fabricated together with a 200-V GaN power switch in a GaN-on-SOI technology. The driver exploits 20-V low-voltage enhancement-mode HEMTs (E-HEMTs), Metal-Insulator-Metal (MIM) bootstrap capacitors and two-dimensional electron gas (2DEG) resistors. To overcome the inherent lack of p-channel devices in the GaN technology, the design employs the bootstrapping approach which allows for full turn-on of the 200-V power GaN switch while minimizing static power consumption. Furthermore, the relatively high breakdown voltage (20 V) of the low-power E-HEMTs allows them to withstand the high voltages generated during bootstrapping. Static power consumption is further reduced by minimizing the number of ratioed logic inverters and implementing an anti-cross-conduction network to eliminate cross-conduction switching losses. The design also leverages the third quadrant of the HEMTs’$I_{\mathrm{DS}}-V_{\mathrm{DS}}$characteristic to emulate the diode behavior, potentially reducing external component requirements. Measured performance reveals an average gate driver current consumption ranging from$370 \mu \mathrm{~A}$at -40°C to$150 \mu \mathrm{~A}$at 150°C. Additionally, the rise and fall times when driving the power switch with 365-m$\Omega$on-resistance are respectively 6.5 ns and 3.5 ns at room temperature.
Katia Samperi, Urmimala Chatterjee, Stefaan Decoutere, Salvatore Pennisi
IEEE Trans. Circuits Syst. I Regul. Pap.2
2025 60-dB 70-V/μs Three-Stage Op-Amp With Dual Single-Miller Frequency Compensation in GaN-IC Technology
abstract
Modern high-performance electronics is pushing Si technology to its limits. Gallium Nitride (GaN) emerges as a promising alternative due to its superior properties in high-frequency and high-power applications. To fully utilize the fast-switching ability of the GaN technology, monolithic integration is a key. A monolithically integrated GaN power IC (Integrated Circuit) reduces the inductive parasitic enabling a fast efficient switching operation. However, GaN basic building blocks, particularly operational amplifiers (Op-Amps), face severe challenges due to the limitations of the GaN technology. This paper presents the first three-stage Op-Amp for high-performance feedback circuits realized in the IMEC’s 200-V GaN-IC technology on a GaN-on-SOI (Silicon on Insulator) substrate. The design utilizes a cascade of three differential stages resistively loaded to achieve a nearly 60-dB DC gain and 25-MHz gain-bandwidth and implements a novel dual single-Miller frequency compensation technique to provide closed-loop stability. The Op-Amp offers a Slew Rate exceeding 70 V/μs with 1% settling time of about 120 ns at room temperature. The correct circuit functionality from −40 °C to 150 °C was demonstrated through simulations and experimental test.
Katia Samperi, Urmimala Chatterjee, Salvatore Pennisi
IEEE Trans. Circuits Syst. I Regul. Pap.2
2014 Design of an intra-module DC-DC converter for PV application: Design considerations and prototype
abstract
The effective efficiency of a photovoltaic system is strongly affected by varying factors such as partial shading. The centralized power conversion has limitations to mitigate that problem. As a possible solution the benefits of the distributed power conversion are explored and as an integral part of distributed power conversion an intra-module DC-DC converter is presented here to implement at substring level in photovoltaic application. In this work, the design requirements of the intra-module converter are identified and the converter is designed accordingly. The effectiveness of the designed converter is also discussed in this paper. Finally, a fully-working prototype of this converter is built and tested.
Urmimala Chatterjee, Ratmir Gelagaev, Alex Masolin, Johan Driesen
IECON1