In this work, we introduce the BRISC-V Toolbox, a register-transfer level (RTL) tool for architecture design space exploration. The BRISC-V Toolbox is an open-source, parameterized, synthesizable set of RTL modules for designing RISC-V based single and multi-core architecture systems. The toolbox is designed with a high degree of modularity. It provides highly parameterized, composable RTL modules for fast and accurate exploration of different RISC-V based core complexities, multi-level caching and memory organizations, system topologies, router architectures and routing schemes. BRISC-V can be used for both RTL simulation and FPGA based emulation. The hardware modules are implemented in synthesizable Verilog using no vendor-specific blocks. The toolbox includes a GCC RISC-V compiler tool-chain to assist in developing software for the cores and a web based system configuration graphical user interface (GUI). The BRISC-V Toolbox supports a myriad of RISC-V architectures, ranging from a simple single cycle processor to a multi-core SoC with a complex memory hierarchy and a network-on-chip. The modules are designed to support incremental additions and modifications. The module interfaces are carefully designed to enable an arbitrary pipeline depth and changes to a single module without impacting the rest of the system. The BRISC-V platform allows researchers to quickly instantiate complete working RISC-V multicore systems with synthesizable RTL correctness and make targeted modifications to fit their needs.