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Wonyeong Jung

dblp:215/6703 · DBLP profile ↗
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3ranked-venue papers
0as first author
2since 2021 · last 2024
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware reliability and fault tolerance · 53% Memory systems · 28% Cloud and datacenter computing · 12%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
DRAM
1.022024
Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers · HPCA 2024
Unity ECC: Unified Memory Protection Against Bit and Chip Errors · SC 2023
Cloud and datacenter computing › resource management
datacenter memory management
0.812024
Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers · HPCA 2024
Memory systems › DRAM
DRAM architecture
0.812024
Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers · HPCA 2024
Hardware reliability and fault tolerance › error-correcting codes for memory
chipkill correct
0.712023
Unity ECC: Unified Memory Protection Against Bit and Chip Errors · SC 2023
Hardware reliability and fault tolerance › error-correcting codes for memory
DRAM error correction
0.712023
Unity ECC: Unified Memory Protection Against Bit and Chip Errors · SC 2023
Hardware reliability and fault tolerance
error-correcting codes for memory
0.712023
Unity ECC: Unified Memory Protection Against Bit and Chip Errors · SC 2023
Hardware reliability and fault tolerance › error-correcting codes for memory
on-die ECC
0.712023
Unity ECC: Unified Memory Protection Against Bit and Chip Errors · SC 2023
Hardware reliability and fault tolerance › error-correcting codes for memory
rank-level ECC
0.712023
Unity ECC: Unified Memory Protection Against Bit and Chip Errors · SC 2023
Energy-efficient computing › power management › memory power management
DRAM power reduction
0.212024
Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers · HPCA 2024
Energy-efficient computing
power management
0.212024
Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers · HPCA 2024

Methods — techniques the papers use, named apart from their topics

runtime mode transition · 0.8syndrome reuse · 0.7error correction codes · 0.7compression · 0.7
YearPublicationVenuePosition
2024 Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers
abstract
Data centers frequently face significant memory under-utilization due to factors such as infrastructure overprovisioning, inefficient workload scheduling, and limited server configurations. This paper introduces Agile-DRAM, a novel DRAM architecture that addresses this issue by flexibly converting the under-utilized memory capacity into enhanced latency performance and reduced power consumption. Through minor modifications to the conventional DRAM architecture, Agile-DRAM supports multiple operational modes: low-latency, lowpower, and the default max-capacity mode. Notably, Agile-DRAM facilitates agile transitions between these modes in response to workload fluctuations in data centers at runtime. Evaluation results demonstrate that the low-latency mode can boost singlecore execution speed by up to 25.8% and diminish energy usage by up to 22.4%. Similarly, the low-power mode can reduce DRAM standby and self-refresh power by 31.6% and 85.7%, respectively.
Jaeyoon Lee, Wonyeong Jung, Dongwhee Kim, Daero Kim, Junseung Lee, Jungrae Kim
HPCA2
2023 Unity ECC: Unified Memory Protection Against Bit and Chip Errors
abstract
DRAM vendors utilize On-Die Error Correction Codes (OD-ECC) to correct random bit errors internally. Meanwhile, system companies utilize Rank-Level ECC (RL-ECC) to protect data against chip errors. Separate protection increases the redundancy ratio to 32.8% in DDR5 and incurs significant performance penalties. This paper proposes a novel RL-ECC, Unity ECC, that can correct both singlechip and double-bit error patterns. Unity ECC corrects doublebit errors using unused syndromes of single-chip correction. Our evaluation shows that Unity ECC without OD-ECC can provide the same reliability level as Chipkill RL-ECC with OD-ECC. Moreover, it can significantly improve system performance and reduce DRAM energy and area by eliminating OD-ECC.
Dongwhee Kim, Jaeyoon Lee, Wonyeong Jung, Michael B. Sullivan 0001, Jungrae Kim
SC3
2017 Morphological Transformation and Force Generation of Active Cytoskeletal Networks
abstract
Cells assemble numerous types of actomyosin bundles that generate contractile forces for biological processes, such as cytokinesis and cell migration. One example of contractile bundles is a transverse arc that forms via actomyosin-driven condensation of actin filaments in the lamellipodia of migrating cells and exerts significant forces on the surrounding environments. Structural reorganization of a network into a bundle facilitated by actomyosin contractility is a physiologically relevant and biophysically interesting process. Nevertheless, it remains elusive how actin filaments are reoriented, buckled, and bundled as well as undergo tension buildup during the structural reorganization. In this study, using an agent-based computational model, we demonstrated how the interplay between the density of myosin motors and cross-linking proteins and the rigidity, initial orientation, and turnover of actin filaments regulates the morphological transformation of a cross-linked actomyosin network into a bundle and the buildup of tension occurring during the transformation.
Tamara Carla Bidone, Wonyeong Jung, Daniel Maruri, Carlos Borau, Roger D. Kamm, Taeyoon Kim 0002
PLoS Comput. Biol.2