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Tian-Xin Yan

dblp:215/9927 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Internet architecture and protocols · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet architecture and protocols › packet processing
packet classification		 0.112005
Design and implementation of packet classification with FPGA (abstract only) · FPGA 2005
Reconfigurable computing and FPGAs › FPGA-based network processing
FPGA-based packet classification		 0.112005
Design and implementation of packet classification with FPGA (abstract only) · FPGA 2005

Methods — techniques the papers use, named apart from their topics

pipelined searching engines · 0.1hicuts algorithm · 0.1
YearPublicationVenuePosition
2005 Design and implementation of packet classification with FPGA (abstract only)
abstract
Even with HiCuts algorithm, which is one of the most effective algorithms for packet classification, the on-line searching for each input packet still consumes the main CPU a large amount of computation resource if it is fulfilled by software. An effective alternative is to use a hardware co-processor to realize the on-line searching. Based on the principle of HiCuts algorithm, the architecture design of a hardware on-line searching co-processor with an FPGA is presented in this paper. Especially, mapping the decision tree and linear search in each leaf node to the memory data structure is described in detail. Benefiting from multiple pipeline structure, there are a total of 12 searching engines working parallel to achieve very high searching speed (8M packet heads/second). The simulation test results show a useful guide for optimization of off-line pre-processing and the co-processor design.
Yong-Gang Wang, Tian-Xin Yan
 FPGA2