A design toolbox based on Matlab-Spectre co-simulation for the automatic design of sub-nanoampere programmable voltage references is proposed. Starting from the MOS devices available in a selected technology, the tool sizes all possible voltage references, for a 3T architecture, minimizing inaccuracy and temperature coefficient, for a given current consumption and power supply rejection. From the best 3T reference, a programmable reference is designed to generate the supply voltage for low power microprocessors with dynamic supply scaling. Our programmable reference achieves a minimum current consumption of 250 pA, with an output voltage range from 0.5 V to 0.95 V. Tested on a 130-nm node, the tool reduces simulator license usage by more than a factor of 1000.

This paper presents a wireless biosensor for in vivo and real-time plant monitoring, with a dedicated remote server, web interface, and cloud data storage. The biosensor is based on a two-wire organic electrochemical transistor nested in the plant stem. When stimulated, the device provides relevant information on the concentration of nutrients in the sap, allowing assessment of the plant health status and early detection of drought stress. The system is based on an ultra-low power circuit interface and a microcontroller with an embedded NbIoT/LTE-M radio. Preliminary results show that the biosensor node can operate under battery for several months, making it suitable for several seasonal crops.

This paper presents a novel write system for memory array with RRAM devices. Our design targets the minimization of the write circuit area and a more compact memory array, by avoiding large-area IO transistors and exploiting the back-gate control in FD-SOI technologies. Indeed, thanks to the Flipped (F)-1T1R cell, replacing the standard 1T1R for the data storage, read and write peripheral circuits, on the columns, can be designed with core devices, to withstand the low reset voltage, for a reduced column pitch. Designed in a 22-nm FD-SOI technology, without IO devices, our write system can safely provide a forming voltage above 3 V and a reset voltage of 1.35 V, with very low values of leakage current. From the optimized layout, we obtained an area ratio, between the write system and the full memory, below 10%, for a memory array with 400 rows and columns.

This paper proposes a dual-output Sample-and-Hold (SH) ultra low-power programmable voltage reference (SH-PVR). Our mixed-signal system regulates the ripple voltage on the output channels due to the leakage current, by monitoring the amplified ripple on a channel replica. The refresh frequency of the references is minimized for the minimum current consumption, while maintaining the ripple specification. Designed and implemented in TSMC 180-nm CMOS technology, the SH-PVR provides two references, with a programmability range [0.5 - 2]$\mathbf{V}$, and a step size of 50 mV. The system achieves a current consumption of 330 nA, with an output ripple below 10$\mu \mathbf{V}$, and it is suitable for ultra low-power devices for IoT, wearable, and implantable applications.

This paper proposes an analytical model for the optimized design of a switched-capacitor programmable voltage reference (SC-PVR). This PVR topology guarantees a straightforward design, easy portability across different technology nodes, and does not require any special technology option. The developed model allows the study of the trade-offs and the a priori evaluation of the system performance. The circuit design optimization is carried out with MATLAB, and it permits SC-PVR to achieve current consumptions of few tens of nanoampere, with a voltage ripple specification of 500 μV. An SC-PVR has been designed in 65-nm CMOS technology, with a sizing extracted by the model optimization. Transistor-level simulation results are aligned with MATLAB results and confirm that the investigated architecture is suitable for ultra low-power applications.

This paper proposes a novel architecture for the generation of a programmable voltage reference: the background-calibrated (BC)-PVR. Our mixed-signal architecture periodically calibrates a static ultra low-power voltage reference generator, from an accurate bandgap reference. The portion of the chip used for the calibration can be powered down with a programmable duty-cycle. The system aims to fully exploit the small temperature derivative vs time$D_{T}$of several application domains to minimize the average current consumption. The BC-PVR has been designed and implemented in TSMC 55-nm CMOS technology, and it achieves the largest reported programming reference output range [0.42 - 2.52] V, over the temperature range [−20, 85] °C. The duty-cycle mode allows nanoampere current consumption, and the large design flexibility permits to optimize the system performance for the specific application. These features make the BC-PVR very well-suited for power-constrained electronic systems.

This paper presents a tiny charge injection-Successive Approximation (ci-SAR) A/D converter (ADC) to be integrated at the periphery of analog Matrix Vector Multiplication (MVM) accelerators for Deep Neural Network (DNN) inference. Derived from the ci-SAR ADC, this converter exploits a single charge injecting cell to minimize area and energy consumption. The ADC exhibits a signal-to-noise and distortion ratio of 30.5 dB, at 5 bits of nominal resolution. The energy per conversion is 86 fJ, running at 34 MS/s, with a silicon area of $75 \mu m ^{2}$, in 22 nm technology node. From the results of our analytical framework, an SRAM-based Analog in-Memory Compute (AiMC) array, including the proposed ADC at 5 bits of resolution, can achieve an energy efficiency of 1650 TOPs/W.

Large weight variations cause significant degradation in Deep Neural Networks (DNNs) accuracy in machine learning (ML) context. Indium-Gallium-Zinc-Oxide (IGZO) DRAM compute cell is a promising option for Analog in-Memory Computing (AiMC) accelerators, but its applicability requires the compensation of large variations affecting the voltage threshold of the readout device. This paper proposes a write-verify scheme for IGZO-based AiMC accelerator, designed in 22-nm technology, based on a compensation loop operating on the analog weight value stored in the IGZO DRAM cell. After the compensation routine, the IGZO IONnormalized variation drops from $\pm \mathbf{2 7} \%$ to $\pm 3 \%$ in simulation. With sufficiently large weight reuse, the additional energy spent for the compensation of the entire arrays becomes negligible, recovering the 2000 TOPS/W baseline performance of an ideal IGZO array without the write-verify.

This paper presents a switched-capacitor Sigma-Delta modulator designed in 90-nm CMOS technology, operating at 1.2-V supply voltage. The modulator targets healthcare and medical diagnostic applications where the readout of small-bandwidth signals is required. The design of the proposed A/D converter was optimized to achieve the minimum power consumption and area. A remarkable performance improvement is obtained through the integration of a low-noise amplifier with modified Miller compensation and rail-to-rail output stage. The manuscript also presents a set of design equations, from the small-signal analysis of the amplifier, for an easy design of the modulator in different technology nodes. The Sigma-Delta converter achieves a measured 96-dB dynamic range, over a 250-Hz signal bandwidth, with an oversampling ratio of 500. The power consumption is$30~\mu \text{W}$, with a silicon area of 0.39 mm2.

Analog in Memory Computing (AiMC) based neural network acceleration is a promising solution to increase the energy efficiency of deep neural networks deployment. However, the quantization requirements of these analog systems are not compatible with state-of-the-art neural network quantization techniques. Indeed, while the quantization of the weights and activations is considered by modern deep neural network quantization techniques, AiMC accelerators also impose the quantization of each Matrix Vector Multiplication (MVM) result. In most demonstrated AiMC implementations, the quantization range of MVM results is considered a fixed parameter of the accelerator. This work demonstrates that dynamic control over this quantization range is possible but also desirable for analog neural networks acceleration. An AiMC compatible quantization flow coupled with a hardware aware quantization range driving technique is introduced to fully exploit these dynamic ranges. Using CIFAR-10 and ImageNet as benchmarks, the proposed solution results in networks that are both more accurate and more robust to the inherent vulnerability of analog circuits than fixed quantization range based approaches.

This paper describes the design of a temperature sensor in 65-nm CMOS technology, intended for food monitoring in IOT and RFID contexts. The digitally-assisted readout scheme combined with a reduced design complexity in the PNP BJT sensor analog front-end allows the minimization of the power consumption. The full sensor occupies an area of 0.26 mm2, with an inaccuracy of ±0.37oC over the [-20oC÷80oC] temperature range, and a power consumption lower than 15.5 μW with a conversion speed of 30 ms.