Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Navid Rahimi

dblp:216/3011 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Processor architecture and microarchitecture · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
high-level synthesis
0.412019
μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators · MICRO 2019
Electronic design automation › design representation
intermediate representation
0.412019
μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators · MICRO 2019
Processor architecture and microarchitecture
microarchitecture optimization
0.412019
μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators · MICRO 2019

Methods — techniques the papers use, named apart from their topics

intermediate representation transformation · 0.4
YearPublicationVenuePosition
2019 μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators
abstract
Creating high quality application-specific accelerators requires us to make iterative changes to both algorithm behavior and microarchitecture, and this is a tedious and error-prone process. High-Level Synthesis (HLS) tools [5, 10] generate RTL for application accelerators from annotated software. Unfortunately, the generated RTL is challenging to change and optimize. The primary limitation of HLS is that the functionality and microarchitecture are conflated together in a single language (such as C++). Making changes to the accelerator design may require code restructuring, and microarchitecture optimizations are tied with program correctness.
Amirali Sharifian, Reza Hojabr, Navid Rahimi, Sihao Liu, Apala Guha, Tony Nowatzki, Arrvindh Shriraman
MICRO3