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Youra Choi

dblp:216/3443 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Storage systems · 100%
Databases, data mining, and information retrieval
1 paper
Transaction processing and concurrency control · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems › non-volatile memory storage
byte-addressable storage
0.312018
2B-SSD: The Case for Dual, Byte- and Block-Addressable Solid-State Drives · ISCA 2018
Storage systems › flash and SSD
solid-state drive
0.312018
2B-SSD: The Case for Dual, Byte- and Block-Addressable Solid-State Drives · ISCA 2018
Storage systems › i/o architecture › i/o subsystem
storage interfaces
0.312018
2B-SSD: The Case for Dual, Byte- and Block-Addressable Solid-State Drives · ISCA 2018
Transaction processing and concurrency control
logging
0.112018
2B-SSD: The Case for Dual, Byte- and Block-Addressable Solid-State Drives · ISCA 2018

Methods — techniques the papers use, named apart from their topics

memory-mapped i/o · 0.7dual address space mapping · 0.7
YearPublicationVenuePosition
2018 2B-SSD: The Case for Dual, Byte- and Block-Addressable Solid-State Drives
abstract
Performance critical transaction and storage systems require fast persistence of write data. Typically, a non-volatile RAM (NVRAM) is employed on the datapath to the permanent storage, to temporarily and quickly store write data before the system acknowledges the write request. NVRAM is commonly implemented with battery-backed DRAM. Unfortunately, battery-backed DRAM is small and costly, and occupies a precious DIMM slot. In this paper, we make a case for dual, byte- and block-addressable solid-state drive (2B-SSD), a novel NAND flash SSD architecture designed to offer a dual view of byte addressability and traditional block addressability at the same time. Unlike a conventional storage device, 2B-SSD allows accessing the same file with two independent byte- and block-I/O paths. It controls the data transfer between its internal DRAM and NAND flash memory through an intuitive software interface, and manages the mapping of the two address spaces. 2B-SSD realizes a wholly different way and speed of accessing files on a storage device; applications can access them directly using memory-mapped I/O, and moreover write with a DRAM-like latency. To quantify the benefits of 2B-SSD, we modified logging subsystems of major database engines to store log records directly on it without buffering them in the host memory. When running popular workloads, we measured throughput gains in the range of 1.2X and 2.8X with no risk of data loss.
Duck-Ho Bae, Insoon Jo, Youra Choi, Joo Young Hwang, Sangyeun Cho, Daniel D. G. Lee
ISCA3