Noise-shaping successive approximation register (NS-SAR) ADCs combine high resolution with energy efficiency, but their performance degrades at bandwidths in the tens of MHz due to limited oversampling ratios (OSR) and adoption of low-order passive filters. This work introduces a$3{^{\text {rd}}}$-order NS-SAR ADC that leverages a multi-input amplifier and a multi-input comparator, enabling independent optimization and flexible filter coefficient sizing. In addition, a ratio-based floating inverter amplifier ensures remarkable gain stability across process, voltage, and temperature (PVT) variations. Implemented in a 28-nm CMOS process, the prototype achieves 12.3-ENOB over a 20-MHz bandwidth while consuming 1.56 mW, resulting in a Schreier figure-of-merit (FoMS) of 177-dB with robust and consistent performance across PVT corners.

This paper analyses for the first time from a quantitative standpoint the effectiveness of redundancy in successive approximation register (SAR) analog-to-digital converters (ADCs) that employ the conventional and monotonic switching algorithms. It is shown that the redundancy tolerance window is one-sided in the case of conventional switching algorithm, thus only underestimations of the input signal can be corrected. Conversely, the monotonic switching algorithm shows a symmetric tolerance window that allows the correction of both underestimations and overestimations of the input signal. Thermal noise due to switches and comparator, and supply bouncing cause both these errors and they can be effectively corrected only with a symmetric redundant window. Behavioral simulations confirm that the monotonic switching algorithm applied to redundant SAR ADCs achieves better performance than the conventional one in terms of signal-to-noise-and-distortion ratio (SNDR).

This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digital locking loop that avoids look-up table (LUT) and finite state machine-based (FSM) locking schemes. Measurements show that the output signal spot noise at 20 MHz from the carrier is −150.7 dBc/Hz while the best locking time, for a coarse step of 364 MHz, is 115$\mu \text{s}$, overcoming the locking time limitations and avoiding cycle slips that usually affect the 1-bit phase detector PLL.