This paper presents a behavior-level approach to improve the SQNR of incremental zoom ADCs with low hardware costs. The digital outputs of the L-th incremental zoom ΔΣ modulator are decimated using an (L+1)-th cascade-of-integrator (CoI) filter. The final quantization error is reduced through accumulating the original quantization error and then averaging. Moreover, the tonal component in the quantization error of zoom architectures is mitigated by injecting Gaussian dithering at the coarse SAR ADC input. Simulation results reveal that a dithered 2nd-order 5-bit incremental zoom ADC can achieve 114.5dB SQNR with a 3rd-order CoI decimation filter, showing a 7dB improvement over the architecture without this method. The resulting hardware overhead is only capacitors for dithering and DFFs in the digital filter, hardly raising any requirement for the analog circuit blocks.

This article presents a two-stage pipelined noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converters (ADCs) for sub-micro-watt and high-resolution applications. However, it asks for an accurate residue amplification to avoid severe quantization noise leakage from the frontend stage. Therefore, a charge-efficient correlated-level-shifting (CECLS) assisted residue amplifier (RA) is designed by inserting the level-shifting network (LSN) in a two-stage floating inverter amplifier (FIA). In addition to the inherited low-power merit from FIA, it boosts the equivalent open-loop gain to 92 dB while preventing bandwidth reduction and charge-sharing effects, making the amplification more accurate and faster than prior CLS-assisted amplifiers. The prototype is fabricated using 55 nm CMOS technology and occupies an active area of 0.26 mm$^{\mathbf {2}}$. The measurement results show a 96.2 dB peak-SNDR and 871 nW power consumption under a 1.2 V supply voltage with a 16 kS/s sampling rate. Compared to the recent state-of-the-art ADCs with power under$10\mu $W and SNDR exceeding 90 dB, this ADC presents the best Schreier FoM of 180.8 dB.

Radio map estimation (RME) is a crucial method for analyzing spectrum space utilization and network coverage, serving as an essential tool for the mobile communication. However, physical constraints, security, privacy, and other issues often render some areas inaccessible, resulting in extremely sparse and unevenly distributed measurement data. To address these challenges, we propose a multimodal feature fusion graph convolution network (MFFGCN). The model incorporates a dual-encoder architecture with an adaptive multi-feature fusion module to exploit environmental information and learn the shadowing effects of radio-signal propagation. We then convert the coarse estimation into regional feature patches and construct a graph over these patches. A graph neural network aggregates contextual information among them, thereby alleviating the impact of uneven spatial sampling. Extensive experiments on open datasets demonstrate that our method achieves state-of-the-art performance, effectively reducing the effects of uneven sampling.

This work proposes a floating-inverter-amplifier (FIA) based high-precision dynamic zoom ADC for low-voltage battery-powered applications. A capacitive biasing technique is proposed to reboot the FIA under low voltages, which enables the FIA to operate under a near-threshold supply voltage. Furthermore, correlated-level-shifting (CLS) is employed to boost the DC gain of the FIA to 51 dB. Simulated in 55nm CMOS under a 0.5V supply, the zoom ADC achieves 84.3dB SNDR while only consuming 723nW at a signal bandwidth of 1kHz. This corresponds to a state-of-the-art Schreier figure-of-merit (FoM) of 175.7 dB.

This paper presents a novel two-stage amplifier, which cascades a duty-cycled inverter-based OTA and a floating-inverter amplifier (FIA). The proposed OTA-FIA can achieve 72.0dB gain under a 1.2V supply, whose output swing is 420mV. Additionally, it exhibits intrinsic loop stability without compensation and reduces thermal noise during integration. The proposed OTA-FIA is adopted in a low distortion 1-1-1 MASH structure to obtain high resolution. Simulated in a 55 nm CMOS process, the proposed ADC can achieve an SNDR of 94.6dB with a bandwidth of 50kHz. It consumes$363.8\mu \mathrm{W}$from a 1.2V supply at a 5MS/s sampling frequency, resulting in a 176.0dB SNDR-based Schreier FoM.