Reconfigurable Intelligent Surfaces (RISs) are emerging as a key technology for enhancing wireless communications in smart city environments, offering robust, low-latency connectivity. This paper presents the design of an adaptive control system based on high-voltage, mixed-signal integrated circuits for controlling tunable RISs, tailored for wireless cellular communications in urban areas. The proposed system enables enhanced programmability by dynamically steering beams and fine-tuning signal reflections through the precise control of varactor diodes embedded within the RIS unit cells. This flexible system architecture supports real-time software reconfiguration, allowing RIS units to adapt to varying network conditions and scale seamlessly across smart city infrastructures. Simulated results on a 0.35 μm CMOS high voltage process technology demonstrate the circuit's ability to achieve low power consumption and high reconfiguration speed across a wide temperature range. The control electronics are separated from the RIS panels, this way enabling tiling of multiple surfaces for scalable, cost-effective deployment. This approach offers a promising pathway to meeting the growing demand for seamless, high-speed, and energy-efficient connectivity in next-generation smart city applications, including vehicular networks, Internet of Things, smart traffic management and smart infrastructure.

Reconfigurable intelligent surfaces (RISs) are recognized as a fundamental enabler for improving energy efficiency in 6G and future networks. However, the power consumption and the reconfiguration delay still need improvement for what is required at GHz frequencies, thus delaying their commercial adaptation. On that regard, this study proposes the incorporation of Integrated Circuits (ICs) with MOS varactor loadings as part of the RIS framework, to improve power consumption and speed, while having precise tuning of the reflection phase for individual unit-cells. The presented circuit design features an asynchronous digital circuit responsible for transmitting binary streams to digital-to-analogue converters, which in turn, bias MOS varactors that are directly connected to each unit-cell within the RIS. The use of asynchronous digital control circuits facilitates the development of ultra-low power, high-speed ICs, thereby enhancing the dynamic scalability of the RIS system. Simulated results of the asynchronous circuit are presented on a mature, cost-effective, CMOS 0.18 μm process technology, showing static power consumption of 40,63 μW, dynamic energy consumption of 474.43 pJ and reconfiguration delay of 23.38 ns. The simulations are accompanied by a scalability analysis and a discussion of potential capabilities, offering valuable insights for the future of ICs on RIS systems. The proposed approach and circuit provide flexibility and performance to RIS systems not achievable with conventional control systems due to their benefits of using clockless networking communication.

Worst-case dI/dt voltage noise is typically characterized post-silicon using direct voltage measurements through either on-package measurement points or on-chip dedicated circuitry. These approaches consume expensive pad resources or suffer from design-time and run-time overheads. This work proposes an alternative non-intrusive, zero-overhead approach for post-silicon dI/dt voltage noise characterization based on sensing CPU electromagnetic emanations using an antenna and a spectrum analyzer. This approach is based on the observation that high amplitude electromagnetic emanations are correlated with high resonance-induced voltage-noise. This approach enables essential Power-Delivery Network characterization tasks such as: a) obtaining the first-order resonance-frequency of the Power-Delivery LC-tank network, and b) automatically generating voltage noise (dI/dt) stress tests with a genetic-algorithm that is driven by the electromagnetic signal amplitude. The generality of the approach is established by successfully applying it to four different CPUs: two ARM multi-core mobile CPU clusters hosted on a big.LITTLE configuration, one x86-64 AMD desktop CPU and one ARM 64bit 8-core clustered architecture server CPU. The efficacy of the proposed methodology is validated through VMINand direct voltage-noise measurements. Furthermore, the effectiveness of the EM approach to generate dI/dt viruses that have higher VMINthat conventional workloads is demonstrated with a dynamic-voltage-scaling (DVS) governor that scales the voltage according to the VMINof the EM generated dI/dt viruses for various core-allocations scenarios. For a 62-hour test with a varying workload mix and core allocations, this governor provides safe below nominal-voltage operation.

Chua's mem-components are ideal for creating adaptive metasurfaces for manipulating EM waves given that they hold their state without external biases. In this paper, we propose a generic adaptive reactive element that is in fact a memcapacitor/meminductor. This element makes use of a polymer that demonstrates reversible trans-cis photochemical isomerization, thus making it possible to change the distance between two conductive plates by up to 25%. Furthermore, a design methodology for utilizing these devices is presented.

A tunable metasurface absorber is presented in this work using an optically-programmable capacitor as the tuning element. The tuning element does not employ conventional semiconductor technologies to operate but rather a bases its tuning by changing the optomechanical properties of its dielectric, poly disperse red 1 acrylate (PDR1A). Doing so there are no conventional semiconductor devices in the RF signal path. The metasurface operates at a design frequency of 5.5 GHz and it achieves an optically-tuned bandwidth of 150 MHz, from 5.50 GHz to 5.65 GHz.

Worst-case dI/dt voltage noise is typically characterized post-silicon using direct voltage measurements through either on-package measurement points or on-chip dedicated circuitry. These approaches consume expensive pad resources or suffer from design-time and run-time overheads. This work proposes an alternative non-intrusive, zero-overhead approach for post-silicon dI/dt voltage noise generation based on sensing CPU electromagnetic emanations using an antenna and a spectrum analyzer. The approach is based on the observation that high amplitude electromagnetic emanations are correlated with high voltage noise. We leverage this observation to automatically generate voltage noise (dI/dt) stress tests with a genetic-algorithm that is driven by electromagnetic signal amplitude and to obtain the first-order resonance-frequency of the Power-Delivery LC-tank network. The generality of the approach is established by successfully applying it to three different CPUs: two ARM multi-core mobile CPU clusters hosted on a big.LITTLE configuration and an ×86-64 AMD desktop CPU. The efficacy of the proposed methodology is validated through VMIN and direct voltage noise measurements.