In the pursuit of advancing computational lithography, this paper introduces a novel pattern database framework designed to support related tasks. The proposed framework is built upon three core components: an unsupervised metric learning method for robust pattern embedding, a vector database for swift pattern retrieval, and an efficient algorithm dedicated to pattern clustering. These elements synergize to significantly enhance the efficiency and effectiveness of various computational lithography methods. In downstream tasks, our framework provides accurate lithography hotspot detection through pattern retrieval, streamlines inverse lithography technique (ILT) by leveraging solution reusing, and facilitates the exploration of ILT & source parameters based on the pattern clustering results. Collectively, these advancements culminate in a comprehensive improvement in computational lithography, offering a scalable solution for the ever-evolving demands of this field.

Inverse Lithography Technology (ILT) is an important Resolution Enhancement Technology (RET) in chip manufacturing. Due to the high computational demands of ILT, large-scale layouts are typically partitioned into smaller tiles for independent processing. In this paper, we propose a multigrid-Schwarz method to overcome challenges in tile assembly. Experimental results show that our approach achieves comparable performance to the full-chip ILT, offering increased parallelizability and speedup in parallel mode. Unlike the traditional divide-and-conquer algorithm, it effectively alleviates discontinuities of tile stitching, preventing manufacturing failures.

Inverse Lithography Technology (ILT) is a widely investigated method to improve the yield of chip manufacturing. However, high computational complexity and difficulty in fabricating curvilinear shapes have hindered the widespread adoption of ILT. This paper presents an efficient ILT framework, including a multi-level resolution method for simulation acceleration, a downsampling strategy for mask optimization, and an improved mask binary function to improve mask printability. Experimental results show that the proposed method outperforms state-of-the-art methods with at least a 33.8% reduction in L2 loss and a 15.5% reduction in PVBand.

Lithography hotspot detection is of great importance in chip manufacturing. It aims to find patterns that may incur defects in the early design stage. Inspired by the success of deep learning in computer vision, many works convert layouts into images, turn the hotspot detection problem into an image classification task. Traditional graph-based methods consume fewer computer resources and less detection time compared to image-based methods, but they have too many false alarms. In this paper, a hotspot detection approach via the graph neural network (GNN) is proposed. We also propose a novel representation model to map a layout to one graph, in which we introduce multi-dimensional features to encode components of the layout. Then we use a modified GNN to further process the extracted layout features and get an embedding of the local geometric relationship. Experimental results on the ICCAD2012 Contest benchmarks show our proposed approach can achieve over 10x speedup and fewer false alarms without loss of accuracy. On the ICCAD2020 benchmark, our model can achieve 2.10% higher accuracy compared with the previous approach.

Lithography hotspot detection is of great significance in chip manufacturing. Hotspots are those patterns that may cause fatal defects in the final tape-out, such as short or open circuits. Therefore, identifying and eliminating hotspots in the early design stage can improve chip yield and reduce manufacturing costs. Traditionally, lithography simulation is used to detect hotspot patterns. But as the feature size shrinks and the design complexity increases, the lithography simulation of the entire chip requires a longer time overhead, which seriously delays the design cycle. Consequently, many deep learning-based methods have been proposed to accelerate hotspot detection. These approaches all show a good performance in the ICCAD 2012 contest benchmarks. However, deep neural networks are vulnerable to adversarial attacks. In this paper, we propose to generate samples by adjusting the critical distance between polygons in the layout based on existing patterns. Layouts are very sensitive to the distance between polygons, the type of a layout may flip by slight modifications in the distances. These adversarial samples are closer to the decision boundary of neural networks than the original ones. Experimental results show that the accuracy of neural network-based hotspot detectors drops significantly in the dataset formed by generated samples. Adding the generated samples to the training dataset improves the robustness and generalization ability of neural networks.