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Shengyang Mao

dblp:216/7153 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 50% Cloud and datacenter computing · 50%
Network and information security
1 paper
Hardware security and side channels · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › hardware trojan
hardware trojan countermeasure
0.312018
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Reconfigurable computing and FPGAs
coarse-grained reconfigurable architecture
0.312018
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Cloud and datacenter computing
resource management
0.312018
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018

Methods — techniques the papers use, named apart from their topics

triple modular redundancy · 0.7knapsack problem · 0.7dynamic programming · 0.7
YearPublicationVenuePosition
2018 DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures
abstract
Coarse grained reconfigurable architectures (CGRA) have been applied to numerous fields of computing- and data-intensive applications, such as computer vision, baseband communication, and cipher processing. A CGRA usually comprises hundreds of reconfigurable computing-cells (RCC), which account for a majority of the die area. As such, RCCs have a higher probability of being attacked by hardware Trojans, which seriously affects CGRA behavior. However, a CGRA can be dynamically and partially reconfigured via configuration contexts at runtime; this property could be utilized as an effective countermeasure against malicious hardware. This particular topic has yet to undergo significant research. This paper proposes a secure mapping approach called dynamic resource management based on security value (DRMaSV) to enhance CGRA capability against hardware Trojans by selectively protecting RCCs. DRMaSV realizes run-time monitoring based on an adapted triple modular redundancy mechanism under hardware resource constraints (i.e., area constraints). First, in order to measure the capability against hardware Trojans, a security capability metric called “security value” (SV) is defined, with measurements categorized as “Influence” and “Unreliability.” Here, both the circuit architecture and the level of Unreliability for modules used in the circuit are considered. Next, a DRM strategy to maximize the SV under hardware resource constraints is introduced. This strategy is described by the dynamic programming model (i.e., 0/1 knapsack problem), which can obtain an optimal solution. Finally, a mapping approach for CGRAs is derived by attaching the DRM strategy to a generic mapping flow. Simulations show that the proposed secure mapping approach ensures a given number of correct outputs, which then allows the number of outputs affected by activated Trojans under any given hardware resource constraint (area constraint) or overhead (area overhead) to be minimized. The results of actual chip design experiments are in agreement with the simulation results, indicating that the proposed secure mapping approach is effective.
Leibo Liu, Zhuoquan Zhou, Shaojun Wei, Min Zhu 0001, Shouyi Yin, Shengyang Mao
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.6