High-speed dynamic latch comparators are integral part of the state-of-the-art ADCs. This work presents a configurable dual-mode voltage comparator using a supply boosting technique. The power dissipation of the comparator is proportional to the square of the supply voltage. Hence, the comparator is configured to operate at a supply voltage of 0.9 V under normal operating conditions. During high-performance mode, when the input differential voltage is small, the supply voltage is boosted to 1.5 V, satisfying the power-delay trade-off. The architecture is designed and simulated in a 180-nm CMOS technology with a supply voltage of 0.9 V. The increased supply voltage of 1.5 V is generated internally using a switched capacitor technique. The power consumed at 0.9 V and 1.5 V is 0.4 mW and 1.29 mW, respectively. The simulated offset at ΔVIN= 1 mV in Mode = 0 and Mode = 1 turns out to be 4.05 mV and 3.14 mV respectively.

This paper presents an energy-efficient level shifter, which up-convert to 1.2 V from 0.3 V. The proposed architecture is based on single-stage differential cascode voltage switch logic (DCVSL) with multi-threshold transistors. A self-adapting pull-up (PU) network is used, which increases the switching speed and reduces energy consumption. To further improve the energy efficiency, a split-input inverting buffer with a higher threshold voltage is used in the output stage. The proposed design is implemented in 65 nm CMOS technology for$V_{DDL}=300\text{mV}$and$V_{DDH}=1.2$V. To up-convert from 0.3 V to 1.2 V, the proposed architecture has an average propagation delay of 11 ns and achieves 3.85 fJ of energy per transition at 1 MHz operating frequency.

This paper presents a novel approach to obtain rational bi-orthogonal wavelet filter coefficients based on Perfect Reconstruction (PR) in Half-Band Polynomial (HBP) by removing Vanishing Moments (VM). A delta-error approach is adopted to design wavelet filter coefficients that reduce the error using an iterative method. This error equation is formulated in terms of generalized HBP, where the odd values are equated to zero and the filter coefficients are constrained with complete dyadic conditions. This produces a generalized design for bi-orthogonal filter with perfect reconstruction. Furthermore, in order to realize power-efficient designs, we propose a reversible logic based implementation for the proposed bi-orthogonal wavelet filter bank. The implementation efficiency is measured in terms of Gate Count (GC), Quantum Cost (QC), Ancilla Input (AI) and Garbage Output (GO). The proposed Design 2 is able to reduce (GC, QC, AI, GO) by (34.3%, 31.6%, 33.9%, 31.1%) when compared to existing design. The effectiveness of the proposed wavelet Filter Banks (FBs) is verified using an image compression application. The experimental results show that, the proposed rationalised wavelet FBs are able to achieve an average increase of 16% in PSNR when compared to existing designs.

This paper proposes a dual ramp, pulse position modulation analog-to-digital converter. A delay cell is proposed in this work, which converts the timing information into a thermometric code. The proposed architecture uses a dual ramp, which initiates the time to digital quantization from both Most Significant Bit (MSB) and Least Significant Bit (LSB) ends. It requires the use of two current sources at both the ends resulting in more symmetrical non-linearity behavior compared to single-ramp architecture, thus improving the INL of the ADC. This technique leads to an increase in the sampling frequency by a factor of 2. It is designed and implemented in a 65-nm CMOS technology with a supply voltage of 1-V. The proposed ADC achieves an effective number of bits of 4.49 bits at a sampling rate of 100 MHz.

This study presents the implementation of image kernels used for filtering and enhancing the images using reversible logic gates, a first in reversible logic literature. Image enhancement/filtering is achieved by performing convolution of an image with a filter kernel. This work proposes reversible logic based design and implementation of six filter kernels. The filter kernels implemented are Gaussian blur, Laplacian outline, Sobel, Emboss, Sharpen and Prewitt edge detection. The kernels are implemented individually using reversible logic gates and the designs are measured in terms of quantum cost, garbage outputs, ancilla inputs and gate count. The functional verification is carried out using standard images on Kintex 7 FPGA platform. The filtered images from the proposed design have an average structural similarity index of 0.92.

To explore the benefits of approximate computing, this article proposes an approximate partial product generator for squarer (APPGS). Using APPGS, three designs of approximate radix-4 Booth squarers (ABS1, ABS2, and ABS3) are proposed. APPGS produces approximate partial products in r number of least significant columns of the partial product matrix. ABS2 and ABS3 utilize approximate adders and compressors with a novel input signal rearrangement method for the accumulation of approximate partial products. Moreover, the ABS3 features an error recovery module at k number of most significant columns of the approximate partial products. The proposed squarers with different values of r and k are simulated using 45-nm CMOS technology. The results indicate that the proposed squarers achieve optimized performance for both hardware and accuracy metrics. Compared to the exact Booth squarer, the 16-bit ABS1 with r = 16 achieves a reduction of 13.6%, 22.2%, and 13.7% in power, delay, and area, respectively, with a normalized mean error distance (NMED) of 4.6 × 10-6. The ABS2 has power, delay, and area savings of 25.8%, 33.8%, and 19.8%, respectively, with an NMED of 7.2 × 10-6. The ABS3 with k = 6 has 18.5% reduction in power, 29.4% reduction in delay, and 16.9% reduction in area with an NMED of 0.56 × 10-6. The performance of the proposed squarers is evaluated with a telecommunication application, where the ABS3 with k = 6 produces an output signal with a signal-tonoise ratio of 32.45 dB.

This paper presents a lossy gyrator, which is used to implement a universal second order current mode filter. The proposed lossy gyrator uses conventional Second Generation Positive Current Conveyor (CCII+) as a basic building block, which has -3 dB bandwidth of 230 MHz and a total power consumption of 15.31 μW. A universal second order current mode filter is designed using proposed lossy gyrator, which achieves a high cutoff frequency of 18 Hz in low pass mode, a low cutoff frequency of 345 Hz for high pass, and a band pass response with resonating frequency at 90 Hz with a total power dissipation of 57 μW. Simulation is done using standard 180 nm CMOS technology at ±0.5 V supply voltage.

Battery operated IoT sensor based applications require low energy interfacing circuits. This paper proposes an auxiliary circuit, which works on the principle of level-crossing sampling, for such energy aware applications. This circuit generates a power enable clock for the ADC, one of the most power hungry blocks in IoT sensor interfaces. The auxiliary circuit is designed and simulated at the transistor level using a standard 180-nm CMOS technology. The effectiveness of the proposed scheme is demonstrated by using a 5-bit flash ADC as a study case. The proposed auxiliary circuit consumes only 3.52% of the total power budget including the test ADC.

Color space conversion is an age old technique used to achieve ease in processing, feature extraction, compression and storage of image and video data. One such color space conversion is RGB to gray scale conversion. Gray scale representation of images aids in reducing storage space and increasing speed of operation. This paper presents a color space conversion scheme using reversible logic gates. An RGB color space to gray scale color space conversion using color channel averaging method and color space desaturation method is implemented in this paper. Reversible logic/computations have emerged as a major alternative to decrease the power dissipation in digital circuits. Reversible sub modules like 8-bit adder, comparator, shifter etc are used to implement the color space conversion. The implementation of reversible logic circuits was done and the functionality verification was done on Kintex 7 FPGA platform. The results are projected in terms of gate count, ancilla input, garbage output and quantum cost for reversible implementation and in terms of hardware utilization and power for FPGA. The proposed reversible circuit complies with the color conversion standards and can find application in any low power image and video processing applications.

Scaling of MOS technology creates new challenges to the SRAM circuit design, mainly the power dissipation due to leakage current and stability. This work proposes a new asymmetric seven transistor SRAM cell, which performs a reliable read operation and enhances the stability performance. The static voltage noise margin (SVNM) of the proposed architecture is 25.8% more than the basic asymmetric 6T SRAM cell and the leakage power consumption is 63.6% less than the basic asymmetric 6T SRAM cell. The read and write delays are 383 ps and 758 ps respectively. The proposed design is implemented in 65nm CMOS Technology at 0.7 V supply voltage.

A fault aware core mapping on Network on Chip (NoC) requires an understanding the calculation of the functional metrics. The functional metrics are Node Average Distance (NAD), Placing unmapped Vertices Region (PVR) and Weighted Communication Energy(WCE). The traditional method of calculating functional metrics are using unmapped cores, distance and weight. However finding the exact values of the functional metrics is not always easy, particularly when busy cores and failed cores are mapped in the middle of available cores. This paper proposes an energy efficient fault aware core mapping algorithm that maps the cores onto the NoC under communication rate constraints to minimize the total communication energy using functional metrics. The simulation results show that proposed mapping algorithm has higher performance over BMAP, PMAP and NMAP algorithm present in literature by 25%, 42%, and 65% under single fault, 30%, 40%, and 60% under two faults and 40%, 44%, and 55% under four faults respectively.

This paper presents design and experimental results of a second-order, discrete-time, quadrature band-pass ΣΔ modulator targeted for wireless body area networks. The non-conventional architecture locks the intermediate frequency (IF) to the sampling frequency. Measurement results collected from a CMOS 0.18-μm prototype achieves a peak SNR of 55 dB over 100-kHz bandwidth and 40-dB SNR over 2.6-MHz bandwidth for a sampling frequency of 20 MHz with 1.96 mW power dissipation.

This paper presents a new concept for an effective design of quadrature band-pass ΣΔ modulators with built-in Signal Transfer Function (STF) filtering action and discusses the architectural level implementation issues for second and third order modulators based on delay line topologies. The methodology uses an architecture which locks the intermediate frequency (IF) to the sampling frequency for both STF and Noise Transfer Function (NTF). Robustness of the structure against the mismatch is analyzed with interference tones placed in different locations of the receiver spectrum, including the image band. Simulations at the behavioral level verify the architecture implementation and the effectiveness of the approach.

The design of a quadrature bandpass Sigma-Delta (ΣΔ) ADC build by cascading two complex modulator is presented. The utilization of cascading enables the independent control of zeros of the noise transfer function. Design method and simulation results including errors due to non-idealities as well as limits of a fourth order scheme are presented. The flexibility of placing notches at critical frequency and benefits are outlined.

A two stage op-amp with an effective technique to enhance slew-rate and gain is presented. The enhancement is provided by an auxiliary monitor circuit which is activated in slewing conditions, but can contribute to the gain in normal conditions. The amplifier, simulated in a 0.18 Omegam technology, achieves 74 dB DC gain, 160 MHz bandwidth and 26.8 V/mus slew-rate for a load capacitance of 1.75 pF with 362 muW power consumption, considering a supply voltage of 1.8 V.