Caching technology is widely used in multiple areas particularly in distributed computing, where its performance is highly dependent on the cache efficiency. The cache eviction algorithm serves as the core component of a cache, primarily aimed at improving cache efficiency by reducing the cache miss ratio. Numerous eviction algorithms are proposed in recent decades and state-of-the-art methods tend to adopt lazy promotion and quick demotion designs. Lazy promotion simplifies cache-hit operations for higher throughput, while quick demotion effectively filters the low-popularity objects. However, the two designs either fail to identify burst objects or suffer from unstable demotion precision. In order to address the above problems, we propose FIFO-MEP, an efficient FIFO cache with Multiple Eviction Points. The key design of FIFO-MEP is to introduce multiple fixed-position eviction points near the head of a FIFO queue. These eviction points enable repeated inspections of objects, leading to effective identification of burst objects. Meanwhile, by fixing positions of these eviction points, FIFO-MEP delivers stable demotion precision. We implement FIFO-MEP using libCacheSim and evaluated it on 5439 production traces for three typical cache sizes, and further verify its efficiency based on Memcached. The evaluation results show that FIFO-MEP reduces the miss ratio by an average of 15.8 % across all experimental configurations. Compared to the state-of-the-art S3-FIFO, FIFO-MEP achieves cache efficiency improvement by up to 21.8 % for large cache sizes. Furthermore, FIFO-MEP yields the best performance under 51 % of all tested conditions.

In high-performance ultra-scale cloud computing, heterogeneous clusters consisting of x86 and ARM architecture platforms have become increasingly common to boost performance and energy efficiency. Ensuring high availability in these environments is crucial for meeting service-level agreements. However, DRAM failures, a primary cause of server downtimes, present significant challenges to reliability, availability, and serviceability. This paper provides an in-depth analysis of memory failure characteristics across cross-architecture platforms in large-scale heterogeneous clusters. We introduce MemSeer, an AIOps-integrated tool that utilizes a multi-grained memory failure prediction approach for x86/ARM heterogeneous clusters. MemSeer improves the F1-score by 17.3% and increases recall by an average of $27 \%$ across different lead times compared to state-of-the-art methods. These advancements show great promise in reducing memory failures in cluster environments, decreasing VM interruptions by up to 42.7% and averaging 24.2% in real-world implementations.

Compute eXpress Link (CXL) offers an effective interface for connecting CPUs with external computing and memory devices. CXL Memory eXpander Controller (CXL-MXC) is gaining attention for its ability to boost memory capacity and bandwidth more efficiently than traditional DDR DIMMs. Despite extensive research on MXC performance and adaptation, DRAM reliability in CXL architecture remains underexplored. Traditional fault tolerance mechanisms like replica or RAID-based systems would significantly increase bandwidth overhead in the CXL fabric, adversely affecting system performance. To address this, we propose the on-CXL-Memory-Expander-Controller ECC (CXL-ECC), by using Locally Recoverable Codes (LRC) as the Inter-Channel-ECC (IC-ECC) and offloading its process to the expander, we eliminate extra memory access requests in the CXL fabric. Consequently, we conduct several experiments to demonstrate that our approach enhances DRAM reliability by more than $10^{9}$, compared to state-of-the-art ECC methods. Relative to RAID-enabled CXL switch, it reduces additional bandwidth overhead from 63.5% to 3.4% and improves system performance by 12%.

Hardware prefetching is one of the most widely-used techniques for hiding long data access latency. To address the challenges faced by hardware prefetching, architects have proposed to detect and exploit the spatial locality at the granularity of spatial region. When a new region is activated, they try to find similar previously accessed regions for footprint prediction based on system-level environmental features such as the trigger instruction or data address. However, we find that such context-based prediction cannot capture the essential characteristics of access patterns, leading to limited flexibility, practicality and suboptimal prefetching performance. In this paper, inspired by the temporal property of memory accessing, we note that the temporal correlation exhibited within the spatial footprint is a key feature of spatial patterns. To this end, we propose Gaze, a simple and efficient hardware spatial prefetcher that skillfully utilizes footprint-internal temporal correlations to efficiently characterize spatial patterns. Meanwhile, we observe a unique unresolved challenge in utilizing spatial footprints generated by spatial streaming, which exhibit extremely high access density. Therefore, we further enhance Gaze with a dedicated two-stage approach that mitigates the over-prefetching problem commonly encountered in conventional schemes. Our comprehensive and diverse set of experiments show that Gaze can effectively enhance the performance across a wider range of scenarios. Specifically, Gaze improves performance by $\mathbf{5. 7 \%}$ and 5.4% at single-core, 11.4% and $\mathbf{8. 8 \%}$ at eight-core, compared to most recent low-cost solutions PMP and vBerti.

Compute Express Link (CXL) enables scalable memory disaggregation, allowing multiple hosts to share a global memory pool. However, existing CXL pooling designs require manual static configuration, underutilize link bandwidth, and suffer from performance unfairness among hosts with diverse memory intensities. This paper presents FAI-CXL, a hardwareaccelerated CXL memory pool unified management architecture that integrates fine-grained, weighted interleaving and adaptive fairness-aware scheduling into the CXL switch. The proposed interleaving mechanism operates at cacheline granularity, improving both link and device bandwidth utilization, while the scheduling policy dynamically adjusts priorities to mitigate unfairness under imbalanced workloads. We implement FAI-CXL in a cycle-accurate ChampSim + Ramulator simulation framework with realistic CXL protocol modeling. Across diverse workload sets, FAI-CXL achieves up to 21 % IPC improvement and 17 % throughput gain compared to conventional pooling approaches, while ensuring fair performance across heterogeneous hosts.

UCEs (Uncorrectable memory errors) pose significant challenges to cloud computing systems, often resulting in catastrophic failures and crashes. Researchers have explored prediction approaches to address this issue. Previous studies have provided insights into memory error prediction, focusing on memory module part numbers and relationships between error code data. However, these efforts face challenges due to insufficient data features and suboptimal optimization, especially in production environments where hardware/software sparing techniques are widely deployed, the UCE ratio is low, and long lead time is required. To address these issues, our study first collect a large amount of memory data from different vendors in Huawei's production environment, which has deployed hardware/software sparing techniques, to provide more general data. Second, we exploit new indicators termed UPH (Unique, Pinx, and History) from this data, which play a crucial role in predicting UCEs. UPH offers a more profound understanding of the factors contributing to UCEs and demonstrates higher precision and recall. Then, we integrate existing indicators and UPH into our prediction framework and demonstrate the significance of UPH through indicator importance assessments. We also optimize the framework by determining an optimal sampling window. In production environments with long lead time and low UCE ratio, we improve the framework by implementing noise reduction, self-history learning, and a new scenario-based model selection approach. Experimental results demonstrate 19 % - 27 % increase in UCE prediction recall with 4 %-11 % increase in precision under different scenarios, outperforming state-of-the-art methods in production environments.

Data compression is increasingly employed to enhance throughput and space efficiency in flash-based storage systems, which are critical for data-intensive applications. Current intra-SSD compression techniques operate transparently with respect to the file system and contribute to improving the lifetime of SSDs. These approaches typically avoid compressing read-hot data to reduce the latency penalties associated with decompression. However, the read-hot data remain uncompressed even after turning into cold data, thereby reducing overall compression effectiveness and diminishing space efficiency. Moreover, when previously compressed cold data become read-hot, it necessitates frequent decompression, which increases the read latency. To address the above problems, we propose a novel Garbage Collection aided Compression (GCC) scheme, to optimize space efficiency and mitigate read latency for compression-supported SSDs. The key idea of GCC is exploiting the valid page migration during garbage collection to enable background compression and decompression. Throughout the garbage collection process, the migrated valid pages can potentially be compressed or decompressed, which progressively improves space efficiency and minimizes the need for decompression during read operations. Performance evaluations conducted using MQSim simulator demonstrate that, compared to the typical compression schemes, GCC reduces the read and write latency by 25.27% and 9.43% on average and improves the space efficiency by 15.01% on average.

Memory deduplication techniques are widely used to improve memory utilization in cloud computing platforms, and they can be categorized into virtualized and containerized environments. In virtualized environments, prevalent memory deduplication approaches often rely on scanning the virtual address space of different processes. However, the complexity of virtual address spaces can reduce scanning efficiency in containerized environments. Additionally, the many-to-one mapping between virtual and physical pages can decrease the efficiency of merging operations.To solve the above problems, we proposed a Container-based Kernel Samepage Merging method called CKSM. This method leverages potential duplicate candidates and efficiently performs merging operations. It employs layered sampling to construct the priority of physical pages. Additionally, a physical page scanning mechanism is designed to directly obtain valid pages within the system. CKSM uses the physical page merge mechanism to merge all virtual pages at once and release the corresponding memory directly. We conduct several experiments to demonstrate the efficiency of CKSM. It reduces the scanning overhead by up to 80.99% and increases page comparison efficiency by up to 42.51%. Besides, CKSM achieves an average of 3.02×memory usage reduction compared to UKSM and 2.79×response speedup compared to KSM in the containerized environment. In cloud computing emulation, CKSM has been proven to be optimal in high-density deployment.

Recently, the flash-based Solid State Drive (SSD) array has been widely implemented in real-world large-scale clusters. With the increasing number of users in upper-tier applications and the burst of Input/Output requests in this data explosive era, data centers need to continuously scale up to meet real-time data storage needs. However, the classical disk array scaling methods are designed based on HDDs, ignoring the wear leveling and garbage collection characteristics of SSD. This leads to penalties due to the vast lifetime gap between extended SSDs and the original in-use SSDs while scaling the SSD array, including extra triggered wear leveling I/O, latency in average response time, etc.To address these problems, we propose an Adaptive Wear-Leveling aware data migration approach for flexible SSD array scaling in clusters. It manages the interdisk wear leveling based on Model Reference Adaptive Control, which includes an SSD behavior emulator, Kalman filter estimator, and adaptive law. To demonstrate the effectiveness of this approach, we conducted several simulations and implementations on actual hardware. The evaluation results show that Ada-WL has the self-adaptability to optimize the wear leveling management parameters for various states of SSD arrays, diverse workloads, and scaling performed multiple times, significantly improving performance for SSD array scaling.

In the recent storage market, Flash-based Solid State Drives (SSDs) have become high-performance alternatives to Hard Disk Drives (HDDs), dramatically increasing SSD shipments. To guarantee product reliability and quality to remain competitive, SSD manufacturers pay significant efforts in technology qualification and reliability design, especially in Manufacturing Self-Test (MST) processes. However, the cost of the MST process becomes more prominent as the memory density of SSD increases. In this paper, we study the MST data in over 20,000 SSDs and propose a novel and economical approach to dynamically reduce the MST overhead by proactive infant defect prediction based on Generative Adversarial Network-Attention based Spatial-Temporal Sequence-to-Sequence network (GAN-ASTSeq). It reduces the temporal cost by 80.2% (i.e., improves the efficiency by 4×) while maintaining an outstanding detection rate of defects.

The straggler problem is one of the most significant problems in cloud computing systems, in which a large number of parallel processes are blocked by a small set of straggler tasks with a long waiting time. This problem is crucial in erasure coded storage systems, where the recovery processes require to retrieve a set of multiple chunks among different nodes. With skewed data accesses from various applications, several nodes with a high workload could easily become stragglers during the recovery process, leading to unacceptable long tail latency. To address the above problems, we propose a Redirection Computational Scheduling method called RCS, to accelerate the data recovery under straggler scenarios. The key idea of RCS is transferring the computational and network workload from one node to another, which can avoid the adverse effects caused by the stragglers. To demonstrate the effectiveness of RCS, we conduct several experiments in a cluster. The results show that, compared to the state-of-the-art recovery methods, RCS saves the recovery time by up to 72.1%, and speeds up the recovery throughput by up to a factor of 1.4X, respectively.

Erasure coding (EC) has been widely used in cloud storage systems to provide both high reliability and low storage cost. Previous literatures show that the cross-rack update operations are prevalent for many applications in erasure-coded cloud storage systems, which introduces significant I/O amplification, load imbalance and high latency. Several existing methods have been proposed to mitigate these problems. However, they ignore the correlations among chunks when performing data placement. Thus numerous stripes and racks participate in the update leading to extra I/Os and cross-rack traffic. Moreover, they don’t take into account the parallelism of network transmission which loses the potential update performance gains.To address the issues, we propose a novel Graph-based cross-Rack Parallel Update (GRPU) scheme to improve the update performance for erasure-coded cloud storage systems. The key idea of GRPU is to place the correlated chunks in the same stripe and rack, and transmit the chunks in parallel based on the network distance. The data placement and transmission paths selection are guided by two kinds of graphs. To demonstrate the effectiveness of GRPU, we conduct several experiments in a local cluster. The results show that, compared to the state-of-the-art methods, GRPU reduces the cross-rack traffic by up to 34.66% and the average response time by up to 61.69%, respectively.

Distributed deep learning is a typical machine learning method running in distributed environment such as cloud computing systems. The corresponding training, validation and test datasets are very large in general (e.g., several TBs), which need to be stored across multiple data nodes. Due to the high disk failure ratio in cloud storage systems, one of the critical issues for distributed deep learning is how to efficiently tolerate disk failures in the training procedures. These failures can lead to a large amount of data loss, which decreases the training accuracy and slows down the training process. Although several recovery methods are proposed to accelerate the data reconstruction, the related overhead is extremely high, such as high CPU/GPU utilization, a large number of I/Os, etc.To address the above problems, we propose a novel Partial-Recovery Method (called PRM) , which is an adaptive recovery method to accelerate data reconstruction for distributed deep learning applications in cloud storage systems. The key idea of PRM is combining the advantages of erasure coding’s ability to obtain global information on the data distribution with the AI’s ability to recover partial lost data, which can sharply reduce the overhead with acceptable training accuracy. To demonstrate the effectiveness of the PRM approach, we conduct several experiments. The results show that, compared to the state-of-the-art full or approximate recovery methods, PRM decreases the average network transmission time overhead by up to 64.50%, and reduces the recovery time by up to 55.90%, respectively.

Nowadays wide stripe erasure codes (ECs) become popular as they can achieve low monetary cost and provide high reliability for cold data. Generally, wide stripe erasure codes can be generated by extending traditional erasure codes with a large stripe size, or designing new codes. However, although wide stripe erasure codes can decrease the storage cost significantly, the construction of lost data is extraordinary slow, which stems primarily from high cross-rack overhead. It is because a large number of racks participate in the construction of the lost data, which results in high cross-rack traffic. To address the above problems, we propose a novel erasure code called XOR-Hitchhiker-RS (XHR) code, to decrease the cross-rack overhead and still maintain low storage cost. The key idea of XHR is that it utilizes a triple dimensional framework to place more chunks within racks and reduce global repair triggers. To demonstrate the effectiveness of XHR-Code, we provide mathematical analysis and conduct comprehensive experiments. The results show that, compared to the state-of-the-art solutions such as ECWide under various failure conditions, XHR can effectively reduce cross-rack repair traffic and the repair time by up to 36.50%.

Nowadays, Solid State Drive (SSD) arrays have been widely used in commercial big data centers and high-performance storage services. Meanwhile, in the era of explosive data growth, data centers need to implement the array scaling schemes to meet the increasing storage capacity requirements. The existing state-of-the-art scaling methods, such as Round-Robin (RR) and FastScale, aim at ensuring a uniform data redistribution. However, most of them are designed for Hard Disk Drive (HDD) arrays, ignoring lifetime difference among extended and former-used disks, which leads to several additional penalties in SSD arrays. Furthermore, due to the sudden interdisk lifetime disparity, the extended SSD disks trigger frequently wear-leveling operations for controlling the wearing balance into the predefined threshold. These reactions result in inefficient scaling and I/O performance degradation. To address the above problem, we propose a Lazy W ear-L eveling (Lazy-WL) mechanism to reduce the conventional wear-leveling overhead during the scaling process. Its core idea is to reduce the unnecessary intensive wear-leveling migration significantly, via narrowing the difference of program/erase (P/E) cycles among new-added and former deployed disks smoothly and gradually. To demonstrate the effectiveness of this approach, we conduct several simulation via Disksim and real implementation via a Hadoop cluster. The evaluation results show that, compared to the typical inter and intra disk wear leveling methods, Lazy-WL could lower the triggered wear-leveling operations by up to 92.9% and achieve a maximal 85.2% response time reduction, which suggests that Lazy-WL performs a balanced I/O distribution, and maintains high performance of SSD array with high scaling efficiency.

Erasure codes (EC) have become a typical technology for distributed storage systems in place of data replication, providing similar data availability but lower storage cost. However, a great number of data computations and migrations during the EC recovery process bring high I/O and network latency penalties. Although several EC recovery methods have been designed to compromise the recovery penalty with high parallelism, the performance of these schemes was usually bounded by the straggler problems due to the various (I/O) performance among different nodes in the storage system. Moreover, the variation of the access popularity from the upper layer application causes the dynamic load fluctuation and asymmetry upon different nodes, which makes the scheduling more difficult during the recovery. To address the above problem, we propose a dynamic load-balanced scheduling algorithm for straggler recovery called EC-Scheduler. EC-Scheduler adjusts the recovery schedule dynamically with the awareness of continuous load fluctuation on the nodes, guaranteeing high parallelism and load balance ability simultaneously. To demonstrate the effectiveness of EC-Scheduler, we conduct several experiments in a cluster. The results show that, compared to typical recovery schemes such as Fast-PR and EC-Store, EC-Scheduler could achieve a 1.3X speed-up in the recovery process and 10X improvement in recovery load imbalance factor.

Energy-efficient microprocessors are essential for a wide range of applications. While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting. In this paper, we perform reliability analysis of 6T SRAM and discover imbalanced minimum voltage requirements between read and write operations. We leverage this imbalance property in near-threshold processors equipped with voltage boosting capability by proposing an opportunistic dual-supply switching scheme with a write aggregation buffer. Our results show that proposed technique improves energy efficiency by more than 18% with approximate 8.54% performance speed-up.

Clean images are an important requirement for machine vision systems to recognize visual features correctly. However, the environment, optics, electronics of the physical imaging systems can introduce extreme distortions and noise in the acquired images. In this work, we explore the use of reservoir computing, a dynamical neural network model inspired from biological systems, in creating dynamic image filtering systems that extracts signal from noise using inverse modeling. We discuss the possibility of implementing these networks in hardware close to the sensors.