Often suffering from under-optimization, Networks-on-Chip (NoCs) heavily impact the efficiency of domain-specific Systems-on-Chip. To cope with this issue, heterogeneous NoCs are promising alternatives. Nevertheless, the design of optimized NoCs satisfying multiple performance objectives is extremely challenging and requires significant expertise. Prior works failed to combine many objectives or required an extended design space exploration time. In this paper, we propose an approach based on generative artificial intelligence to help pruning complex design spaces for heterogeneous NoCs, according to configurable performance objectives. This is made possible by the ability of Generative Adversarial Networks to learn and generate relevant design candidates for the target NoCs. The speed and flexibility of our solution enable a fast generation of optimized NoCs that fit users' expectations. Through some experiments, we show how to obtain competitive NoC designs reducing the power consumption with no communication performance or area penalty compared to a given conventional NoC design.

A Network-on-Chip (NoC) is an essential component of a chip multiprocessor (CMP) which however contributes to a large fraction of system energy. The unpredictability of traffic across a NoC frequently involves an expensive over-sizing of NoC resources which in turn leads to a significant contribution to the CMP power consumption. There exists a body of work addressing this issue, however so far solutions fall short when aiming for power reduction whilst maintaining high NoC performance. This paper proposes to combine router architecture optimizations with smart resource management to overcome this limitation. Based on a fully segmented architecture, we present an online adaptive router adjusting its active routing resources to meet the current traffic demand. This enhanced power-gating strategy significantly decreases both static and dynamic power consumption of the NoC, up to 70% for synthetic traffic patterns and up to 58% for real traffic workloads, while preserving NoC latency and throughput. Thanks to these adaptive power-saving mechanisms the proposed segmented NoC router provides near energy-proportional operation across the range of used benchmarks.

Multi-core systems are now found in many electronic devices. But does current software design fully leverage their capabilities? The complexity of the hardware and software stacks in these platforms requires software optimization with end-to-end knowledge of the system. To optimize software performance, we must have accurate information about system behavior and time losses. Standard monitoring engines impose tradeoffs on profiling tools, making it impossible to reconcile all the expected requirements: accurate hardware views, fine-grain measurements, speed, and so on. Subsequently, new approaches have to be examined. In this article, we propose a non-intrusive, accurate tool chain, which can reveal and quantify slowdowns in low-level software mechanisms. Based on emulation, this tool chain extracts behavioral information (time, contention) through hardware side channels, without distorting the software execution flow. This tool consists of two parts. (1) An online acquisition part that dumps hardware platform signals. (2) An offline processing part that consolidates meaningful behavioral information from the dumped data. Using our tool chain, we studied and propose optimizations to MultiProcessor System on Chip (MPSoC) support in the Linux kernel, saving about 60% of the time required for the release phase of the GNU OpenMP synchronization barrier when running on a 64-core MPSoC.

Each generation of shared memory Multi-Processor System-on-Chips (MPSoCs) tend to embed more and more computing units. The cores of modern MPSoCs are often grouped into clusters communicating with each other through Networks on Chip (NoCs). Having efficient scalable synchronization mechanisms is then mandatory to benefit from the high parallelism they offer.In this work we propose an innovative hardware support for synchronization locks. First of all, a non-intrusive measurement tool-chain allows us to prove a fundamental hypothesis as to optimization of the lock mechanism: although a lock may be used, at runtime, by various cores belonging to different clusters, it is often reused by the last core which has released it. Based on this observation, we provide a hardware decentralized solution to manage dynamic re-homing of locks in a dedicated memory, close to the latest access-granted core. This reduces overall access latency and network traffic in case of reuse of the lock within the same cluster.This paper presents our solution, called Lockality, and its performance evaluation on a characteristic MPSoC running on a hardware emulator. Experiments show large gains at low level (physical lock acquisition) as well as at the application level.

Providing high-performance synchronization mechanisms is a key issue to benefit from hardware parallelism offered by MPSoCs. In this paper, we focus our study on the synchronization barrier mechanism and the impact of hardware contention in shared memory clustered MPSoC. Taking advantage of a new observation methodology based on emulation, we identify Linux kernel sub-optimal services. We show how the introduction of delays in the thread awakening process improves the overall synchronization mechanism resulting in an optimization of the synchronization barrier in passive wait mode providing a large gain: 67% for 64 threads running on a 64-core architecture.

The benefit expected from the hardware parallelism offered by Multi-Processor System on Chips (MPSoCs) is determined by the ability to design high-performance synchronization mechanisms. The complexity of modern MPSoCs does not allow anymore to design an optimized software application without confront it with the hardware platform restrictions. In this paper, we propose a methodology to study the impact of hardware contention in the synchronization barrier mechanism running on a shared memory clustered MPSoC. Taking advantage of this new observation methodology based on emulation, we identify hardware module restrictions and Linux kernel suboptimal services. We show how the introduction of delays in the thread awakening process Improves the overall synchronization mechanism. Then we detail how a combined Hardware/Software optimization for the passive wait of the synchronization barrier provides a large gain: about 60% for 64 threads running on a 64-core architecture.