Skin, the primary regulator of heat exchange, relies on sweat glands for thermoregulation. Alterations in sweat gland morphology play a crucial role in various pathological conditions and clinical diagnoses. Current methods for observing sweat gland morphology are limited by their two-dimensional, in vitro, and destructive nature, underscoring the urgent need for real-time, non-invasive, quantifiable technologies. We proposed a novel three-dimensional (3D) transformer-based segmentation framework, enabling quite precise 3D sweat gland segmentation from skin volume data captured by optical coherence tomography (OCT). We quantitatively reveal, for the first time, 3D sweat gland morphological changes with temperature: for instance, volume, surface area, and length increase by 42.0%, 26.4%, and 12.8% at 43°C vs. 10°C (all p <0.001), while S/V ratio decreases (p =0.01). By establishing a benchmark for normal sweat gland morphology and offering a real-time, non-invasive tool for quantifying 3D structural parameters, our approach facilitates the study of individual variability and pathological changes in sweat gland morphology, contributing to advancements in dermatological research and clinical applications.

The quality of edge computing microservices is significantly influenced by their ability to perceive the spatiotemporal dynamics of user locations. Traditional approaches to microservice deployment in edge environments often rely on manual adjustments based on user position and base station load, which introduces substantial complexity and inefficiency. To address these challenges, we propose a novel methodology for spatiotemporal-aware microservice pre-deployment utilizing large language models (SAMPLE). By leveraging the predictive capabilities of spatiotemporal large language models, our approach enhances the microservice’s spatiotemporal awareness through trajectory forecasting. Additionally, we introduce an automated framework for generating optimal microservice deployment strategies based on the spatiotemporal relationships between users and services. Experimental results demonstrate that the proposed method significantly improves service quality by autonomously sensing user movement and dynamically adjusting deployment strategies, enhancing both the efficiency and responsiveness of edge services. The implementation code and datasets are available at https://github.com/ssea-lab/SAMPLE.

Metal Oxide Thin Film Transistors (MO TFTs), known for their flexibility and low cost, are widely used in wearable electronics and biomedical fields. In these applications, capacitive sensors are important for their high sensitivity and low cost, enabling accurate detection of touch and pressure. To make use of these sensor signals, Capacitive-to-Digital Converters (CDCs) are typically used to convert the signals into digital form. Traditional silicon-based CDCs rely on Switched-Capacitor (SC) circuits, with accuracy primarily determined by high-gain Operational Transconductance Amplifiers (OTAs). However, the lack of high-gain OTAs in TFT technique limits SC-based CDC precision. This paper presents a TFT CDC design using an iterative discharge method, avoiding reliance on OTA gain to enhance accuracy and energy efficiency. The proposed design achieves a 6.2-bit Effective Number of Bits (ENOB) for capacitances up to 100pF in 14ms, with a Figure of Merit (FoM) of 690nJ/c-s. To the best of our knowledge, this is the first comprehensive study on TFT CDCs.

ABSTRACT Chinese painting is the traditional way of painting in China, with distinctive artistic characteristics and a strong national style. Creating Chinese paintings is a complex and difficult process for non‐experts, so utilizing computer‐aided Chinese painting generation is a meaningful topic. In this paper, we propose a novel Chinese painting generation model, which can generate vivid Chinese paintings in a stroke‐by‐stroke manner. In contrast to previous neural renderers, we design a Chinese painting renderer that can generate two classic stroke types of Chinese painting (i.e., middle‐tip stroke and side‐tip stroke), without the aid of any neural network. To capture the subtle semantic representation from the input image, we design a semantic loss to compute the distance between the input image and the output Chinese painting. Experiments demonstrate that our method can generate vivid and elegant Chinese paintings.

Spiking neural networks (SNNs) have shown great potential in achieving high energy efficiency and low power consumption compared to artificial neural networks (ANNs). However, there remains a significant accuracy gap between SNNs and ANNs. To address this issue, we present an in-memory neuromorphic computing (IMNC) chip that supports hybrid spiking/artificial neural networks (S/ANNs) and sparsity-aware data flows. With the IMNC chip, we aim to improve inference accuracy while simultaneously achieving high energy efficiency through optimization at the algorithm, architecture, and circuit levels. First, at the algorithm level, we note that SNNs extract temporal features from input spikes using time-domain convolution operations. Based on this insight, we efficiently utilize leaky integrate (LI) neurons to hybridize SNNs and ANNs, thereby improving accuracy while maintaining highly sparse operations. Second, at the architecture level, we design a sparsity-aware architecture that supports a hybrid S/ANN topology with varying sparsity. Finally, at the circuit level, we propose a ring-based in-memory computing (IMC) macro, whose energy consumption is inversely proportional to the input sparsity, making it ideal for performing energy-efficient multiplication and accumulation (MAC) operations in both SNNs and ANNs. We evaluate the proposed hybrid S/ANNs on various classification tasks and demonstrate their stronger classification and generalization ability compared with pure SNNs. Notably, our IMNC chip, fabricated using 22 nm CMOS technology, achieves impressive measured accuracy rates of over 95% for voice activity detection (VAD) and ECG anomaly detection. Additionally, our IMNC chip demonstrates superior dynamic energy efficiency of 0.43 pJ per synaptic operation, outperforming related works.

In the field of medical image processing, accurate segmentation is of great importance to assist doctors in diagnosis. However, existing machine learning methods are hardly effective for medical image segmentation in the absence of large and accurate datasets. Existing methods of learning with noisy labels rarely try to explore the correlation between noisy and clean labels. We found that some error corrections are learnable in the process of noisy labels corrected by medical experts. In this work, we propose a novel method to improve the performance of medical image segmentation. The method consists of two main networks: segmentation network segments the image and label correction network records and learns the denoising process of noisy labels, denoises the noisy labels. In addition, we introduce a feature fusion branch between the two networks. We compare with several state-of-the-art methods which learning with noisy label on the gastric wall dataset and notice that our method has strong competitiveness.

This paper proposes an information-aware (IA) adaptive data acquisition (ADA) system for the Internet of Things (IoT) applications. The system can obtain valid information adaptively thanks to 1) signal-dependent full-scale feature tracks the amplitude-domain activity of the event; 2) level-crossing (LC) ADC with slope detector delivers the time-domain activity; 3) the IA algorithm determines the quantization resolution according to the detected signal activities. The proposed clock-free event-driven ADA system can reject the redundant data, and compress the valid data from the source, thus saving its power and the power of subsequent data-processing systems. The long-term average power consumption of the system is 128 nW, the resolution varies from 3 to 7 bits according to the input signal state. Compared with conventional ADCs, LC-ADC can compress the data by 2.5x [1]. Further, the proposed system has 15x higher compression ratio (CR) than that of LC-ADC.

Interrupt-driven embedded software is widely used in aerospace, automotive electronics, medical equipment, IoT, and other industrial fields. This type of software is usually programmed with interrupts to interact with hardware and respond to external stimuli on time. However, uncertain interleaving execution of interrupts may cause concurrency bugs, resulting in task failure or serious safety issues. A deep understanding of real-world concurrency bugs in embedded software will significantly improve the ability of techniques in combating concurrency bugs, such as bug detection, testing and fixing.

Interrupt-driven programs are extensively employed in safety-critical areas such as aerospace, autonomous driving, and medical equipment. Nevertheless, the uncertainty of interrupt preemption may result in concurrent bugs. Among these concurrent bugs, atomicity violations are critical and challenging to detect. Existing methods mostly concentrate on predicting or detecting single-variable atomicity violations but fail to address the more intricate multi-variable atomicity violations. In real-world programs, many variables are inherently correlated and must be accessed together with their correlated peers consistently. To significantly improve the ability of techniques in inferring correlated variables, this paper conducts an empirical study on real-world software to understand the manifestation characteristics of variable correlations. Building upon this foundation, an automated method called intCV, based on the XGBoost model, is introduced to effectively infer correlated variables within interrupt-driven programs. Once we accurately identify the correlated variables requiring atomic execution, existing detection techniques can be utilized to identify violations of multi-variable atomicity. Experimental results on real-world aerospace embedded software demonstrate the practicality and effectiveness of our method.

Erasure codes have been widely applied to in-memory key-value storage systems for high reliability and low redundancy. In distributed in-memory key-value storage systems, update operations are relatively frequent, especially the partial-stripe update, which makes data update more challenging. Recently, existing research has been based on appending logs to accelerate parity data write. However, its logs are stored on disks, which decreases the system performance significantly. Therefore, we propose a novel in-memory key-value storage architecture, DNVPL, which utilizes NVRAM to log parity data. Our main idea is to design an appending-only update scheme to tradeoff the memory cost and the update overhead. We implement DNVPL with an in-memory key-value storage prototype, called LogKV. We evaluate it with different workloads. The experiments show that our scheme achieves high update performance from different metrics. Our scheme can reduce update latency by up to 49% and save storage space by 48% compared to the state-of-the-art schemes.

This article presents a clock-free spiking neural network (SNN) intelligent inference engine (IIE) for artificial intelligence of things (AIoT) sensor nodes, which often operate in random-sparse-event (RSE) scenarios. The IIE drastically reduces the system’s long-term average (LTA) power consumption, improves energy efficiency, and achieves microsecond level inference latency. Three techniques are proposed: 1) A clock-free SNN architecture without clock tree, frame generator, and arbiter, is driven by the output spikes, which are encoded with level-crossing (LC) sampling method; the circuit activity is completely related to event activity and spike rates, dramatically reducing the overall power consumption and latency. 2) The bioinspired leaky-integrate-fire (LIF) neurons directly extract the time-domain information from asynchronous spikes, reducing the network size and number of operations. 3) The computing-in-memory (CIM) and mixed-signal synapse-neuron circuits are employed to increase the SNN parallelism and avoid weight movements, thus improving the energy efficiency and response speed. The measured LTA power is bounded at 82 nW while the event-driven chip is on call and waiting for events; the energy efficiency is 0.53 pJ per synapse operation (SOP), only 1/3 that of state-of-the-art methods at 4bit weights even with 180 nm technology. We demonstrate electrocardiogram (ECG) recognition as a typical AIoT application, and the power consumption is less than 350 nW. The measured accuracy of abnormal ECG detection is 90.5%. Moreover, the latency is only$40 \mu \text{s}$to realize real-time NN inference. This work provides an effective solution for AIoT nodes that require both ultralow power and fast response.

Dual-polarization radar provides information about precipitation microphysics through drop size distribution and hydrometeor classification, and, therefore, can produce improvement in quantitative precipitation estimation. Rainfall relations combination is an optimization algorithm; however, optimally selecting the rainfall relation is challenging in dual-polarization rainfall estimation. In this study, an adaptive rainfall algorithm is developed using a logistic regression model to guide the choice of the optimal radar rainfall relation. The logistic model is established according to the matched dual-polarization radar data and rain gauge data. Only liquid particles are considered for the rainfall estimation determined by the hydrometeor classification of dual-polarization radar, and the polarimetric rainfall relations are obtained with a neural network algorithm based on the disdrometer data. The proposed algorithm is validated with C-band dual-polarization radar data, and the results show that the adaptive algorithm outperforms the single rainfall relation and conventional combination algorithm.

Tunnel FET is recognized as one of the most promising candidates for ultra-low power applications due to its ultra-low off current and CMOS compatibility. However, some characteristics of TFET caused by asymmetric device structure and special conduction mechanism may make conventional topologies of logic circuits no longer applicable. Our previous work has reported that TFET stacking will result in severe current degradation, which makes traditional logic cells not applicable. In this paper, two solutions are proposed: first, from a logic cell perspective, novel hybrid TFET-MOSFET topologies of standard logic cells are proposed, which achieve more than 2 times lower hardware cost and intrinsic delay, hence up to 4 times lower area-power-delay product (APDP) than that of conventional TFET logic circuits. Compared to MOSFET logic circuits, the designs achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP. Second, from a large-scale circuit perspective, an optimized digital front-end (DFE) is proposed. Taking serial peripheral interface (SPI) as an example, SPI circuit using the optimized DFE achieves 46% lower delay and 4 times lower APDP than that of traditional TFET SPI, and 3 orders of magnitude lower static power and APDP than that of MOSFET SPI.

Power is becoming a major bottleneck in energy constraint applications such as internet-of-things (IoT). Emerging steep-slope devices such as tunnel FETs (TFET) and negative capacitance (NC) FETs are promising candidates for such type of applications. Nevertheless, due to the time-consuming characterization process and inconsistent evaluation criteria, conventional co-design and co-optimization process between novel devices and logic circuits takes too much time and its results rarely meet expectation. As a result, conventional co-design and co-optimization are quite inefficient. In this paper, for the first time, a new criterion is utilized to evaluate novel steep-slope devices for ultra-low power applications. In addition, an efficient evaluation method is proposed, which not only quantitatively guides device design, but also evaluates devices from a circuit perspective without the need for device compact model and circuit simulation. From a device design perspective, optimal design metrics of novel steep slope devices such as average subthreshold slope (SSavg), off current (IOFF), and on current (ION) can be directly figured out with the help of the proposed evaluation criteria and method. From a circuit design perspective, the proposed evaluation criteria and method can be used to determine application scope.

The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.

Tunnel FET (TFET) is recognized to be one of the most promising candidates for ultra-low power applications due to its ultra-low off current and high compatibility with CMOS process. However, different from the typical features of MOSFET, some electrical characteristics of TFETs caused by asymmetric device structure and special conduction mechanism may make conventional topologies of circuits no longer applicable. In this paper, it is found that the TFETs stacking will result in severe current degradation behavior, which makes traditional topologies of logic gates may be not applicable. To solve this problem, a set of novel hybrid TFET-MOSFET topologies for standard logic cells are proposed. The proposed designs achieve more than 2 times lower hardware cost and intrinsic delay, and realize up to 4 times lower area-power-delay product (APDP) than that of conventional TFET-based logic circuits. Moreover, the proposed topologies can achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP than that of conventional MOSFET-based logic circuits. The proposed standard logic cells show great superiority for power-constraint applications.

In this paper, a novel combinational access topology of Tunnel FET (TFET) SRAM is proposed for ultra-Low Power applications. Since forward p-i-n current of TFET could cause serious damage to SRAM circuit performance, the proposed topology can avoid the forward bias applied to the p-i-n junction, thus increasing SRAM cell read and hold static noise margin (SNM) and decreasing its static power consumption dramatically. At 0.6 V supply voltage, the combinational access TFET SRAM topology presents 26% hold SNM larger than traditional TFET SRAM topologies, 8 orders of magnitude lower static power consumption, and 2 order of magnitude lower power delay product, demonstrating its great potential for ultra-low power applications.