Logic built-in self-test (LBIST) suffers from excessive power consumption due to high toggling rates caused by pseudo-random patterns. This paper presents a programmable low-power LBIST scheme that leverages scan chain weighting based on ATPG-guided fault analysis. By analyzing the distribution of specified bits across ATPG-generated test cubes, each scan chain is assigned a weight indicating its relative contribution to fault detection. Chains are then grouped into seven activation levels, each mapped to a distinct toggle probability to balance power and test coverage. A configurable control circuit based on shift and hold registers generates the required low-power signals. Experimental results on industrial-scale designs demonstrate that the proposed method achieves significantly higher fault coverage under identical power constraints compared to a commercial LBIST solution.

The remarkable growth of the circuit size and complexity is primarily due to the advances of VLSI design and manufacturing technologies. The on-chip linear sequential test compression has become the de facto industrial mainstream DFT methodology in reducing the overall cost of testing large chips. In this paper, we propose a novel and efficient compression-aware ATPG method to significantly boost the performance of ATPG and reduce pattern count. The proposed approach first analyzes the intrinsic dependency of the equations determined by a linear sequential decompressor to build Maximal Linear Independent Group (MLIG). Next it computes the implied values given ATPG generated test cubes based on MLIG. The implied values can significantly improve the test compaction and reduce the ATPG run time due to the reduction of value conflicts between ATPG and compression. The proposed approach does not affect test coverage, requires no extra hardware support, and can be applied to any linear sequential compression scheme. Experimental results on several industrial designs demonstrate that on average the proposed approach can reduce the number of ATPG patterns by 7.57% and the ATPG run time by 28.4%.

XORNet-based low power controller is a popular technique to reduce circuit transitions in scan-based testing. However, existing solutions construct the XORNet evenly for scan chain control, and it may result in sub-optimal solutions without any design guidance. In this paper, we propose a novel testability-aware low power controller with evolutionary learning. The XORNet generated from the proposed genetic algorithm (GA) enables adaptive control for scan chains according to their usages, thereby significantly improving XORNet encoding capacity, reducing the number of failure cases with ATPG and decreasing test data volume. Experimental results indicate that under the same control bits, our GA-guided XORNet design can improve the fault coverage by up to 2.11%. The proposed GA-guided XORNets also allows reducing the number of control bits, and the total testing time decreases by 20.78% on average and up to 47.09% compared to the existing design without sacrificing test coverage.