Hyperdimensional computing (HDC) has been recognized as an efficient machine learning algorithm in recent years. Robustness against noise and simple computational operations, while being limited by the memory bandwidth, make it a perfect fit for the concept of computation in memory (CiM) with emerging nonvolatile memory (NVM) technologies. For an HDC accelerator based on NVM-CiM, there are different parameters from the algorithm all the way down to the technology that interact with each other and affect the overall inference accuracy as well as the energy efficiency of the accelerator. Therefore, in this paper, we propose, for the first time, a full-stack co-optimization method and use it to design an HDC accelerator based on NVM-based content addressable memory (CAM). By incorporating the device manufacturing variability and co-optimizing the algorithm and hardware design, HDC inference on our proposed NVM-based CiM accelerator can reduce the energy consumption by 3.27x, while compared to the purely software-based implementation, the inference accuracy loss is merely 0.125%.

Magnetoresistive random access memory (MRAM) is an attractive option to replace eFlash. The recent demonstration of a nano-second write speed and a 10e14 endurance are compelling performances even as an embedded MRAM for cache replacement. Both eFlash and cache applications often use large array sizes, which require tight defect control. The unique defects in MRAMs that are not easily detectable with traditional memory test algorithms can potentially cause test escapes. Test escapes will not only delay the manufacturing process but also cause reliability issues, which is fatal for safety-critical applications such as automotive. This paper presents effective ways of screening hard-to-find defects related to oxide surface quality. The devices with minor oxide degradation have properties in the grey zone, which spec out some of the properties, although they pass the functional test. We introduce a new test method to screen those spec out cells using read reference trimming.

Neural Networks (NN) can be efficiently accelerated in a neuromorphic fabric based on emerging resistive non-volatile memories (NVM), such as Spin Transfer Torque Magnetic RAM (STT-MRAM). Compared to other NVM technologies, STT-MRAM offers many benefits, such as fast switching, high endurance, and CMOS process compatibility. However, due to its low ON/OFF-ratio, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed current and, in turn, degradation of inference accuracy. In this article, we analyze the impact of the sensed accumulated current variation on the inference accuracy in Binary NNs and propose a design-time reference current generation method to improve the robustness of the implemented NN under different temperature and process variation scenarios (up to 125 °C). Our proposed method is robust to both process and temperature variations. The proposed method improves the accuracy of NN inference by up to 20.51% on the MNIST, Fashion-MNIST, and CIFAR-10 benchmark datasets in the presence of process and temperature variations without additional runtime hardware overhead compared to existing solutions.

Deep Neural Networks (DNNs) have gained considerable attention lately due to their excellent performance on a wide range of recognition and classification tasks. Accordingly, fault detection in DNNs and their implementations plays a crucial role in the quality of DNN implementations to ensure that their post-mapping and infield accuracy matches with model accuracy. This paper proposes a functional-level automatic test pattern generation approach for DNNs. This is done by generating inputs which causes misclassification of the output class label in the presence of single or multiple faults. Furthermore, to obtain a smaller set of test patterns with full coverage, a heuristic algorithm as well as a test pattern clustering method using K-means were implemented. The experimental results showed that the proposed test patterns achieved the highest label misclassification and a high output deviation compared to state-of-the-art approaches.

As we move toward the commercialization of Spin-Transfer Torque Magnetic Random Access Memories (STT -MRAM), cost-effective testing and in-field reliability have become more prominent. Among STT-MRAM manufacturing defects, pinholes are one of the important ones. Pinholes are defects on the surface of the oxide layer which degrade the resistive values and, in some cases, cause an oxide breakdown. Some moderate levels of pinhole defects can remain undetected during standard functional tests and may cause a field failure. A stress test of the whole memory, including multiple cycles of long writes, has been suggested to detect candidate pinhole defects. However, this test not only causes extra costs but also degrades the reliability of MRAM for the entire array. In this paper, we have statistically studied the behavior of pinholes and proposed a cost-effective testing scheme to capture pinhole defects and increase the reliability of the end product. Our method limits the number of test candidate cells that need to be hammered, providing a reduced test time of up to 96.42% for our case studies compared to existing methods. This is while the advantages of standard tests are all preserved with our method. The proposed approach is compatible with memory-built-in self-test (MBIST) schemes.

The matrix-vector multiplication (MVM) is one of the most frequent operations performed in deep learning hardware accelerators. The crossbar array structure with memristive devices as a building block has an inherent capability to perform energy-efficient MVM. However, the memristive devices suffer from various non-idealities as well as limited number of stable levels. Therefore, the reliability and in turn inference accuracy of the deep learning application is negatively impacted. Thus, this paper presents a low overhead checksum-based error correction method for memristive crossbars for MVM computation. The proposed methodology alleviates the problem of storing the checksum value into multiple columns of the crossbar due to the limited number of stable levels of memristive devices. The number of extra columns required for storing the checksum value is reduced, resulting in a significant reduction in the memory overhead by up to 75%. The proposed method scales the checksum value of trained neural networks (NNs) and then performs checksum-aware retraining, and results show negligible impact (∼3%) on the inference accuracy of the NNs on MNIST, Fashion-MNIST, CIFAR-10, and Veg-15 datasets.

Neuromorphic computation-in-memory fabric based on emerging nonvolatile memories considered an attractive option to accelerate neural networks (NNs) in hardware as they provide high-performance, low-power, and reduced data movement. Although nonvolatile resistive memories (NVMs) offer many benefits, they are susceptible to data retention faults, where previously stored data are not retained after a certain amount of time due to external influence. These faults are more likely to happen unidirectional and severely impact the inference accuracy of the hardware implementation of NNs since the synaptic weights stored in the NVMs are subject to retention faults. In this work, we propose an approximate scrubbing technique for NVM-based neuromorphic fabric to mitigate unidirectional retention faults with virtually zero storage overhead depending on the definition of scrub area for multilayer perceptron (MLP) and convolutional NNs (CNNs). The training of the NNs is adjusted accordingly to meet the requirements of the proposed approximate scrubbing scheme. On different benchmarks, the proposed scrubbing approach can improve the inference accuracy up to 85.51% for MLP and 87.76% for CNN over the expected device operational time with negligible storage overhead.

Analog Computation-in-Memory (CiM) with emerging non-volatile memories leads to significant performance and energy efficiency. Spin-Transfer Torque Magnetic Memory (STT-MRAM) is one of the promising technologies for CiM architectures. Although STT-MRAM has various benefits, it does not have the potential to be used directly in analog multi-value CiM operations due to its limited levels of cell resistance states. In this paper, we propose a novel flexible multi-value design for STT-MRAM (MVSTT) with the potential to be used for multi-value CiM. In the multi-value CiM, we are able to have various 2sresistive state combinations from$s$selected MTJs, which is not possible in the normal STT-MRAM CiM. The size of the MVSTT can be adjusted at run-time depending on the application's requirements. The benefits of the proposed scheme are quantified in representative applications such as multi-value matrix multiplications, which is the basic computation of Neural Networks applications. For the multi-value matrix multiplication, the energy, and delay gain is up to 9.7 × and 13.3 ×, respectively, to non-CiM matrix-vector-multiplication. Also, for the neural network, the proposed design allows up to a 32 × reduction in the STT-MRAM cells per crossbar to achieve a similar inference accuracy as the binarized neural network.

Neural Networks (NN) can be efficiently accelerated using emerging resistive non-volatile memories (eNVM), such as Spin Transfer Torque Magnetic RAM(STT-MRAM). However, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed state and in turn, degradation of inference accuracy. We propose a design-time reference current generation method to improve the robustness of the implemented NN under different thermal and process variation scenarios with no additional runtime hardware overhead compared to existing solutions.

Emerging non-volatile resistive memories like Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) and Resistive RAM (RRAM) are in the focus of today’s research. They offer promising alternative computing architectures such as computation-in-memory (CiM) to reduce the transfer overhead between CPU and memory, usually referred to as the memory wall, which is present in all von Neumann architectures. A multitude of architectures with CiM capabilities are based on these devices, due to their inherent resistive behavior and thus their ability to perform calculation directly within the memory, and thus without invoking the CPU at all. However, emerging memories are sensitive to Process, Voltage and Temperature (PVT) variations. This sensitivity has an even larger impact on CiM architectures. In this paper, we analyze and compare the impact of PVT variations on STT-MRAM and RRAM-based CiM architectures. We perform a sensitivity analysis to identify which parts of the CiM structure are most susceptible to PVT variations, for each technology. Based on these analyses, we recommend that STT-MRAM is used in high-performance CiM, while RRAM is used for edge CiM.

STT-MRAM has long been a promising non-volatile memory solution for the embedded application space owing to its attractive characteristics such as non-volatility, low leakage, high endurance, and scalability. However, the operating requirements for high-performance computing (HPC) and low power (LP) applications involve different challenges. This paper addresses different aspects of STT-MRAM; it will cover state-of-the-art, some new results and future challenges related to technology, design and test. While STT-MRAM devices have shown encouraging performance metrics at device-level, a key challenge has been achieving backend-of-line (BEOL) CMOS compatibility, while retaining the benefits of low power operation. Scaling demands to improve data densities have placed additional challenges in terms of addressing the impact of process-induced damage on device performance at CD < 100 nm. In addition, the paper discusses the design of reliable read mechanism considering the variability effects. Moreover, the failure of traditional fault modeling and test approaches in model STT-MRAM unique defects for appropriate test solutions is demonstrated in this paper based on silicon data.

Spin-Transfer-Torque Random Access Memories (STT-MRAM) offer attractive features such as high-density, low power consumption and non-volatility. Process variations (PV) are one of the critical problems during the manufacturing process. To mitigate PV, reference trimming is used, to compensate for the offset of the tested array based on their functional behavior. However, additional tests can increase the manufacturing test budget. In this paper, we present a novel approach based on address skipping during the trim search step of the memory test, by accessing only a small sub-array. This enables a significant reduction in trim search time. We perform a progressive skip test flow to improve the overall test time for binary search based trim search by up to 29% while ensuring to capture any failing bits with our proposed skip search.

Neuromorphic architectures based on emerging resistive memories are in the spotlight of today's research as they are able to solve complex problems with an unmatched efficiency. In particular, resistive approaches offer multiple advantages over CMOS-based designs. Most prominently they are non-volatile and offer small device footprints in addition to very low power operation. However, regular memory testing used for conventional resistive Random Access Memory (RAM) architectures cannot detect all possible faults in the synaptic operations done in a resistive neuromorphic architecture. At the same time, testing all neuromorphic operations from the logic testing perspective is infeasible. In this paper we propose to use reference resistance trimming for the test phase and derive a generic test sequence to detect all the faults impacting the neuromorphic operations based on an extensive defect injection analysis. By exploiting the resistive nature of the underlying architecture, we are able to reduce the testing time from an exponential complexity necessary for a conventional logic testing approach to a linear complexity and reduce this by another 50% with the help of resistance trimming.

Neuromorphic computation-in-memory fabric based on emerging non-volatile memories (NVM) is considered an attractive option to accelerate neural networks (NNs) in hardware as they provide high-performance, low-power, and reduced data movement. Although NVMs offer many benefits, they are susceptible to data retention faults, where previously stored data is not retained. This severely impacts the inference accuracy of mapped NNs. Traditionally, memory scrubbing with error-correcting codes (ECC) is employed to mitigate retention faults in conventional CMOS memories. This is not feasible in NVM-based neuromorphic fabric due to high overhead and inability to represent encoding or decoding in analog computing. In this work, we propose an approximate scrubbing technique for NVM-based neuromorphic fabric to mitigate uni-directional retention faults with minimal storage overhead. The training of the NNs adjusted accordingly to meet the requirements of the scrubbing scheme. On different benchmarks, the proposed scrubbing approach can improve the inference accuracy up to 85.51% over the lifetime with virtually zero storage overhead.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the most promising candidates to replace conventional embedded memory such as Static RAM and Dynamic RAM. However, due to the small on/off ratio of MRAM cells, process variations may reduce the operating margin of a chip. Reference trimming was suggested as one of the ways to reduce variation impact to the chip. In addition to process variation, thermal variations reduce the operating margin of STT-MRAM even further and impose a tighter limit on the operating temperature range than CMOS technology. Defects that relate to marginal thermally behavior are especially difficult, because it is very costly to test across the entire operating temperature range at the tester, and can even reduce the lifetime of the chip. Therefore, we propose a Memory Built-in Self Test (MBIST) supported screening method to accurately predict the failure behavior of a device under test at high temperatures solely from lower temperature test. By adding five more BIST runs at 85°C, we are able to predict MRAM failures at 125°C with 99.11% accuracy. This prediction can then be used to define a reference trim adjust value to optimize the read operation across the entire operating temperature range of the MRAM.

Computation in Memory (CiM) promises to significantly improve the efficiency of data-intensive applications. Spin Transfer Torque (STT) magnetic memory, as one of the front-runners in emerging resistive non-volatile memories, is a suitable candidate for the implementation of CiM architectures. However, the much smaller off/on ratio of resistance states compared to other non-volatile memories makes CiM implementation challenging in this technology. This is further exacerbated with asymmetrical process and temperature variations of the resistance states of Magnetic Tunnel Junction (MTJs) and CMOS components, resulting in erroneous CiM operations. In this paper, we perform a detailed technology-aware statistical failure analysis of CiM operation and design the optimal reference circuitry for CiM sensing to minimize the failure rate with respect to process and temperature variations. Our results show that using a simpler model of CiM array is sufficient for the optimization of the sensing circuitry. However, it may lead to over-optimistic estimation of failure rates. Therefore, a more comprehensive model is utilized for accurate estimation of CiM failure rates.

In recent years, computation is shifting from conventional high performance servers to Internet of Things (IoT) edge devices, most of which require the processing of cognitive tasks. Hence, a great effort is put in the realization of neural network (NN) edge devices and their efficiency in inferring a pretrained Neural Network. In this paper, we evaluate the retention issues of emerging resistive memories used as non-volatile weight storage for embedded NN. We exploit the asymmetric retention behavior of Spintronic based Magnetic Tunneling Junctions (MTJs), which is also present in other resistive memories like Phase-Change memory (PCM) and ReRAM, to optimize the retention of the NN accuracy over time. We propose mixed retention cell arrays and an adapted training scheme to achieve a trade-off between array size and the reliable long-term accuracy of NNs. The results of our proposed method save up to 24% of inference accuracy of an MNIST trained Multi-Layer-Perceptron on MTJ-based crossbars.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), as one of the most promising emerging memory technology for on-chip memory, offers many advantageous features such as high density, non-volatility, scalability, high endurance and CMOS compatibility. Additionally, its resistive storage concept can be utilized for Compute-in-Memory (CiM), where bit-wise logical operations can be performed within the memory without the need for transferring the data from the memory to the processor and back. However, these new CiM operations are impacted by defects, resulting in faults which are different from the conventional memory faults. Hence, these CiM specific faults need to be modeled and appropriate test strategies need to be derived to ensure correct functionality of the CiM enabled memories. In this paper, we first perform extensive defect injection in the CiM bit-cell and build fault models based on the impact of the defects. We also compare CiM specific faults to normal memory faults based on this technology. From this model, we derive an efficient test algorithm to fully cover CiM related faults, which cannot be found with conventional memory test algorithms.

Deep neural networks (DNNs) are gaining increasing attention and usage in many fields related to artificial intelligence and cognitive processing. Due to challenges associated with the implementation of DNNs using traditional computing architectures, there is a growing interest for brain-inspired, aka Neuromorphic computing platforms and paradigms for direct and hence more efficient implementation of DNNs. The building blocks and operation mode of circuitry and the architectures for Neuromorphic computing bring new challenges, since the implementation and operation of neural networks is fundamentally different from traditional Boolean logic. From the technology point of view, they are based on emerging non-volatile resistive memories, which have new fabrication processes and steps, and hence subject to new types of defects and failures. This paper addresses technology-specific defect characterization for spintronic-based neuromorphic circuits.

Emerging memristor-based architectures are promising for data-intensive applications as these can enhance the computation efficiency, solve the data transfer bottleneck and at the same time deliver high energy efficiency using their normally-off/instant-on attributes. However, their storing devices are more susceptible to manufacturing defects compared to the traditional memory technologies because they are fabricated with new materials and require different manufacturing processes. Hence, in order to ensure correct functionalities for these technologies, it is necessary to have accurate fault modeling as well as proper test methodologies with high test coverage. In this paper, we propose technology specific cell-level defect modeling, accurate fault analysis and yield improvement solutions for memristor-based memory as well as Computation-In-Memory (CIM) architectures. Our overall contributions cover three abstraction levels, namely, device, architecture and system. First, we propose a device-aware test methodology in which we have introduced a key device-level characteristic to develop accurate defect model. Second, we demonstrate a yield analysis framework for memristor arrays considering reliability and permanent faults due to parametric variations and explore fault-tolerant solutions. Third, a lightweight on-line test and repair schemes is proposed for emerging CIM devices in machine learning applications.

Recently Spin Transfer Torque Random Access Memory (STT-MRAM) technology has drawn a lot of attention for the direct implementation of neural networks, because it offers several advantages such as near-zero leakage, high endurance, good scalability, small foot print and CMOS compatibility. The storing device in this technology, the Magnetic Tunnel Junction (MTJ), is developed using magnetic layers that requires new fabrication materials and processes. Due to complexities of fabrication steps and materials, MTJ cells are subject to various failure mechanisms. As a consequence, the functionality of the neuromorphic computing architecture based on this technology is severely affected. In this paper, we have developed a framework to analyze the functional capability of the neural network inference in the presence of the several MTJ defects. Using this framework, we have demonstrated the required memory array size that is necessary to tolerate the given amount of defects and how to actively decrease this overhead by disabling parts of the network.

As leakage increases proportionally with the technology downscaling, it becomes extremely challenging to manage to meet the total power budget. This is because, CMOS-based logic blocks can not be completely power-gated as their flip-flops always require a retention supply to hold the system states. Alternatively, their data can be stored in a separate memory during the standby mode, however, that results in a huge area and energy overhead. Spin Transfer Torque (STT) based nonvolatile flip-flops can offer normally-off/instant-on computing features to reduce leakage by complete power shut-down without the need to transfer and restore system states separately. The non-volatile component of such flip-flops can be easily shared for the overall design optimizations. In this paper, we design a unique multi-bit non-volatile flip-flop architecture using STT devices to reduce the area and energy costs associated with nonvolatile components. This architecture is developed based on the resource sharing principle using a custom design that enables the optimization for the area and energy consumption. Moreover, we have developed a framework in which we have replaced the conventional neighbor flipflops in the layout with our proposed multi-bit non-volatile designs. Results show that using our multi-bit flip-flop architecture, we improve the system-level area and energy by 26% and 14% in average, respectively, compared to the standard single-bit non-volatile flip-flop design.