This paper proposes a class-C digitally controlled oscillator (DCO) using constantly-conducting NMOS biased switchable capacitor, aiming to optimize the off-state quality factor, reduce the off-state capacitance and improve the oscillator transient behavior. The DCO is fabricated in a 28 nm CMOS technology. With a unitary-weighted SC bank, the DCO shows an inherently monotonic tuning with a range of 8.2-11.1 GHz (30.1%), and a very fine tuning resolution of 40kHz. The class-C DCO achieves -115.5 dBc/Hz phase noise at 1 MHz offset from 10 GHz carrier frequency with 23 mW, resulting in a -182 dBc/Hz FoM and -191.5dBc/Hz FoMT.

Abstract Dynamic linear functions on the boolean hypercube are functions which assign to each bit a positive weight, but the weights change over time. Throughout optimization, these functions maintain the same global optimum, and never have defecting local optima. Nevertheless, it was recently shown [Lengler, Schaller, FOCI 2019] that the $$(1+1)$$ ( 1 + 1 ) -Evolutionary Algorithm needs exponential time to find or approximate the optimum for some algorithm configurations. In this experimental paper, we study the effect of larger population sizes for dynamic binval, the extreme form of dynamic linear functions. We find that moderately increased population sizes extend the range of efficient algorithm configurations, and that crossover boosts this positive effect substantially. Remarkably, similar to the static setting of monotone functions in [Lengler, Zou, FOGA 2019], the hardest region of optimization for $$(\mu +1)$$ ( μ + 1 ) -EA is not close the optimum, but far away from it. In contrast, for the $$(\mu +1)$$ ( μ + 1 ) -GA, the region around the optimum is the hardest region in all studied cases.Kindly check and confirm the inserted city name is correctly identified.Correct.

This paper presents a low-noise low-dropout regulator (LNLDO) implemented in a 28 nm technology. The LNLDO features a two-stage architecture, using a low-pass filter with a very low cut-off frequency to separate the regulation loop and the noisy devices such as resistive divider and bandgap reference. Supplied by a 1.5 V-1.8 V input voltage, the LNLDO is able to provide a stable output voltage ranging from 0.73 V to 1.71 V, with a current supply ability from 0 to 35 mA. An on-chip capacitance enhancer is used to stabilize the regulation loop without an additional external capacitor. The RMS noise from 10 Hz to 100 kHz of the LNLDO is below 20μV.

This paper presents an approach for a system-level noise simulation in the frequency domain for RF systems. The noise analysis is able to depict frequency conversion due to nonlinear or time-varying circuits and can also consider the signal processing in the digital part. Therefore, it is possible to analyze the noise from all parts of the system at a point of choice, e.g. directly at the demodulator input. The approach is based on analog models of the genuine circuit level implementation used for system level exploration or verification purpose. It can be integrated in a conventional system level simulation with nearly no overhead. The noise analysis is implemented on top of an already existing event-driven RF simulation approach which uses a combination of System Verilog and C++ for modeling. MATLAB is used for post-processing and visualization of the results.

Nanoscale CMOS enables and forces the use of digital-centric RF architectures, where timing resolution is traded for analog resolution. Simultaneously, digital circuits act as aggressors endangering the performance of the time continuous digital and analog parts. The switching activities of logic cells result in power supply variations which lead to jitter in the digital signal paths and causes interferers coupling to the analog paths, appearing as e.g. phase noise, crosstalk, unwanted frequency conversion, etc. Since todays commonly used AMS simulation methods are limited to register-transfer level (RTL) models for the digital domain, the electrical behavior caused by digital switching is not considered. Here, a method for modeling logic cells with regard to power supply noise is presented using the available characterization data of a standard cell library. It covers the influence of switching on the supply voltage as well as influences of supply variations on the digital path delay and their feedthrough to blocks of the RF domain. A fast event-driven simulation of an entire AMS system regarding the mentioned aspects is enabled. The method is demonstrated on a digital-centric transmitter to detect the effects on system level.