With the increasing integration of semiconductor design, many problems have emerged. Row-hammering is one of these problems. The row-hammering effect is a critical issue for reliable memory operation because it can cause some unexpected errors. Hence, it is necessary to address this problem. Mainly, there are two different methods to deal with the row-hammering problem. One is a counter based method, and the other is a probabilistic method. This paper proposes the improved version of the latter method and compares it with other probabilistic methods, PARA and PRoHIT. According to the evaluation results, comparing the proposed method with conventional ones, the proposed one has increased row-hammering reduction per refresh 1.82 and 7.78 times against PARA and PRoHIT in average, respectively.

Phase change memory (PCM) is a scalable, non-volatile emerging memory. The storage density of the PCM can be enhanced by using the multi-level cell (MLC) operation. However, the MLC PCM suffers from low reliability due to resistance drift. The rate of resistance drift is proportional to the initial resistance of the cell with intermediate storage levels being particularly vulnerable. Using heavy Error Correction Codes (ECC) results in poor effective storage density (data bits per cell) of the MLC PCM. The state-of-the-art Tri-level cell technique improves reliability by using only three out of four storage levels, thus eliminating the ECC overhead. However, its storage density is much less than the ideal MLC PCM. Moreover, its storage density is fixed even if practically the MLC PCM reliability is improved. This paper introduces a more flexible pattern redistribution technique, Flipcy, to improve the MLC PCM reliability and effective storage density. The proposed method proportions the data-patterns according to the rate of resistance drift for different storage levels. A simple flip or a complement operation is used to reduce the percentage of the most error-prone pattern. The simulation results show up to 107X reduction in the error rate and 31% improvement in performance compared to the conventional MLC PCM. With a reduced overhead of the auxiliary bits and ECC parity bits, the proposed method can achieve about 25% improvement in effective storage density over the Tri-level cell approach for a similar level of reliability while incurring about 11% degradation in performance compared to the Tri-level cell approach. This performance degradation can be reduced when the proposed method is accompanied with orthogonal techniques to improve MLC PCM reliability and efficient scrubbing methods.

Conventional DRAM and flash memory are reaching their scaling limits thus motivating research in various emerging memory technologies as a potential replacement. Among these, phase change memory (PCM) has received considerable attention owing to its high scalability and multi-level cell (MLC) operation for high storage density. However, due to the resistance drift over time, the soft error rate in MLC PCM is high. Additionally, the iterative programming in MLC negatively impacts performance and cell endurance. The conventional methods to overcome the drift problem incur large overheads, impact memory lifetime and are inadequate in terms of acceptable soft error rate (SER). In this paper, we propose a new PCM memory architecture with heterogeneous PCM arrays to increase reliability, performance and lifetime. The basic storage unit in the proposed architecture consists of two single-level cells (SLCs) and one four-level cell (4LC). Using the reduced number of 4LCs compared to conventional homogeneous 4LC PCM arrays, the drift-induced error rate is considerably reduced. By alternating each cell operation between SLC and 4LC over time, the overall lifetime can also be significantly enhanced. The proposed architecture achieves up to 105times lower soft error rate with considerably less ECC overhead. With simple ECC scheme, about 22% performance improvement is achieved and additionally, the overall lifetime is also enhanced by about 57%.