Demo Data from EDBT 2026 / reviewers in the wild / expert
Zixuan Huang 0011
dblp:218/2712-11
· DBLP profile ↗
2ranked-venue papers
1as first author
2since 2021 · last 2025
0009-0006-7121-6775ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Storage systems · 59% Parallel and multicore computing · 36% Processor architecture and microarchitecture · 5% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems
flash and SSD |
1.6 | 2 | 2025 | Expanding Logical Space Freely: A Memory-efficient Mapping Table Design for Compressional SSDs · DAC 2025 PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture · DAC 2024 |
Storage systems › flash and SSD › flash memory management
flash translation layer |
0.9 | 1 | 2025 | Expanding Logical Space Freely: A Memory-efficient Mapping Table Design for Compressional SSDs · DAC 2025 |
Parallel and multicore computing › synchronization
lock-free synchronization |
0.8 | 1 | 2024 | PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture · DAC 2024 |
Parallel and multicore computing
parallel programming models and runtimes |
0.8 | 1 | 2024 | PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture · DAC 2024 |
Processor architecture and microarchitecture
multicore design |
0.2 | 1 | 2024 | PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture · DAC 2024 |
Methods — techniques the papers use, named apart from their topics
promotion and demotion · 0.9n-to-1 mapping · 0.9multi-core request scheduling · 0.8lock-free pipelining · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Expanding Logical Space Freely: A Memory-efficient Mapping Table Design for Compressional SSDsabstractCompressional SSDs can be a mixed blessing. While they offer users expanded logical space beyond the physical capacity, they complicate the Flash Translation Layer (FTL) design by requiring a larger Logical-to-Physical (L2P) address mapping, which places a heavier burden on the limited in-SSD memory, leading to a degraded I/O performance. In this paper, we aim to reduce the memory footprint of the L2P mapping table in compressional SSDs by proposing a novel N-to-1 L2P mapping table design that consolidates multiple logical entries into a single entry. This approach eliminates the duplication of physical page numbers when a physical page contains several compressed logical pages. To accommodate the dynamic compression ratios of real-world workloads, we introduce promotion and demotion that enable mapping table entries to migrate between pages with different compression ratios. Additionally, to address the issue of partial invalidation-where some compressed logical pages within a physical page are invalid due to the N-to-1 mapping-we present a compression-aware garbage collection algorithm aimed at minimizing the number of copy operations for partially invalid physical pages. We have implemented our design in MQsim, a widely used SSD simulator, and have conducted a series of experiments to evaluate the effectiveness of the proposed techniques. The results demonstrate that our approach significantly reduces the mapping table size in compressional SSDs, leading to an improved mapping table cache hit ratio and a reduced I/O latency compared to traditional compressional SSDs. Zixuan Huang 0011, Tianyu Wang 0009, Kecheng Huang, Zelin Du, Zili Shao |
DAC | 1 |
| 2024 | PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core ArchitectureabstractModern SSD firmware is continuously optimized for higher parallelism to match the growing frontend PCIe bandwidth with more backend flash channels. Although a multi-core microprocessor is typically adopted to concurrently process independent NVMe requests from multiple NVMe queues, the existing one-to-many thread-request mapping model with each thread serving one or more incoming I/O requests has poor scalability due to severe lock contention problem, especially in cache management. Zelin Du, Shaoqi Li, Zixuan Huang 0011, Jin Xue, Kecheng Huang, Tianyu Wang 0009, Zili Shao |
DAC | 3 |