High-resolution ADCs require low noise and low distortion while consuming minimal power. This paper presents a power-efficient, calibration-free, 2nd-order noise-shaping (NS) SAR ADC. Mismatch error shaping (MES) is employed to reduce distortion from capacitive DAC mismatches. The resulting input range loss is compensated for by an additional digital prediction (DP) method. To mitigate the high power consumption of the multi-input dynamic comparator, this work proposes a coarse-fine comparison (CFC) scheme, enabling the ADC to switch between SAR and NS-SAR modes. This approach reduces the power consumption of the comparator while maintaining NS functionality. Furthermore, to eliminate the need for an external high-speed clock to control SAR logic and NS operation, this work utilizes a fully asynchronous logic driven solely by a sample-and-hold clock. Implemented in standard 130-nm CMOS technology, this prototype ADC achieves a measured 81.54-dB SNDR (13.25-bit ENOB) in a 100-kHz bandwidth with an oversampling ratio (OSR) of 25.

In addition to the conventional ADC design tradeoffs between power, speed, and accuracy, radiation tolerance is the fourth factor for ADCs used in radiation environments. This paper describes radiation-tolerant (RT) ADC design tradeoffs and design strategies. Then, the paper introduces a 13-bit RT pipelined-successive-approximation register (pipelined-SAR) ADC fabricated in 65 nm CMOS technology based on the concluded tradeoffs. To further improve the ADC power efficiency, a semi-time-interleaved (Semi-TI) structure is employed. Besides, the ping-pong auto-zeroing (AZ) scheme is implemented in the residue amplifier (RA) to reduce the TID-induced offset while maintaining low power dissipation. The proposed ADC is designed and hardened against Single Event Effects (SEEs) and Total Ionizing Dose (TID) effects from the structure to layout levels. All sub-blocks were examined, and only the critical blocks were hardened to avoid over-hardening. From the measurement results, the prototype ADC attains an 80 MS/s sampling rate and achieves 70.8-dB SNDR and 80.3-dB SFDR at the Nyquist input frequency. With a total power consumption of 13.8 mW, the prototype ADC establishes a state-of-the-art Walden Figure of Merit of 60.7 fJ/conv step, yielding an efficiency comparable to non-RT ADCs with similar specifications. Irradiation tests validate the consistent performance of the ADC up to a cumulative dose of 500 krad (Si) in X-ray testing, while laser testing indicates a robust SEE threshold and swift post-SEE recovery.

This paper presents a high-speed readout interface suitable for nanopore-FET (NPFET) sensor arrays, which are being explored for high-throughput DNA or protein sequencing applications. The readout interface utilises a novel architecture that can simultaneously perform recording and automatic background calibration to compensate for offset and drift of the individual NPFET threshold voltages, eliminating the need for a separate calibration step or an area-consuming DAC. A prototype readout IC has been manufactured in 0.18-$\mu \text{m}$CMOS to validate the circuit concepts. It features 32 NPFET interface circuits multiplexed to 8 parallel analog outputs. Each individual channel achieves a bandwidth of 10 MHz. The prototype IC has been characterised experimentally, and the online calibration capability has been validated with liquid-gated FETs in a microfluidics setup.