This work presents a detailed analysis of the impact of MOS device performance on circuit metrics at cryogenic temperatures. An experimentally proven, industry standard compact model is calibrated to match the performance of the corresponding devices from ST Microelectronics 28 nm (STM28) PDK. The temperature related parameters of this model are then calibrated with experimental data at cryogenic temperatures, available in the literature. This model is then used to explore a Strong-Arm latched comparator, a 4-bit Flash ADC and a ring oscillator to study temperature-dependent performance trends. We point out certain key concerns which necessitate additional design effort and area/hardware overhead required to achieve the desired specifications at cryogenic temperatures.

A chopper-stabilized, low-noise bandgap reference (BGR) employing a double-sampled, switched capacitor low pass FIR filter (DS-FIR) is presented. Chopping reduces the low frequency flicker noise, while the FIR filter rejects the high frequency thermal noise. Double-sampling is used to avoid the down-conversion of chopped flicker noise, due to the sampling nature of the switched capacitor filter. Designed in 180-nm CMOS process, the proposed BGR achieves a 5X reduction in flicker noise (at 1 kHz) and 100X reduction in thermal noise (≥ 100 kHz) compared to the basic BGR, with a small area overhead. The entire circuit occupies 0.042 mm2at schematic level.

We investigate the performance degradation of a continuous-time pipelined (CTP) ADC due to the input load presented by the flash sub-converter. It turns out, as we show in this work, that the flash ADC loading affects the alias rejection and the linearity of the CTP. We propose a simple technique to alleviate these problems. The theory is borne out by simulation results from a 100 MHz-bandwidth pipeline ADC designed in a 65 nm CMOS process.

The continuous-time pipeline (CTP) analog-to-digital converter is an emerging technique that combines the benefits of pipelining with continuous-time operation. Prior-art multistage CTP ADCs have employed stages with identical transfer functions. This work proposes the use of non-identical (and appropriately chosen) transfer functions for different stages of the pipeline. We investigate the benefits of this approach when compared with conventional techniques. We also demonstrate that the sharp filtering offered by a multi-stage CTP can be exploited to implicitly decimate the output sequence of the converter. This is accomplished by clocking the back-end ADC at a lower rate, and by appropriately modifying the digital reconstruction filters. The implicit-decimation theory is supported with measurement results from a three-stage CTP designed in a 65nm CMOS process. The converter achieves 70.4dB SNDR in a 100MHz bandwidth with its front-end operating at$f_{s}\,{=}\,800$MHz, while the back-end samples at$f_{s}/2$.

The continuous-time pipelined (CTP) ADC is a promising emerging high-speed analog-to-digital conversion technique that achieves anti-alias filtering and analog-to-digital conversion in one step. Driving such a converter is easy, thanks to its resistive input impedance. RC time-constant shifts, which will occur in practice due to a change in ambient temperature, degrade the performance of such converters. The aim of this work is to understand this phenomenon, quantify the resulting SNDR degradation, and thereby derive design tradeoffs. The theory is compared with measurements from a three-stage CTP that targets 70dB SNDR in a 100MHz bandwidth while sampling at 800MS/s.

We show that the nonlinearity of the first integrator's operational transconductance amplifier (OTA) significantly degrades the alias rejection of a bandpass CTΔEM in the presence of OTA parasitics. We derive the expression for alias rejection when the OTA used in the first integrator is realized as a two stage feed-forward compensated structure. Simulation results confirm the theory.