Andrea Gambero

dblp:219/2706 · DBLP profile ↗
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5ranked-venue papers
0as first author
5since 2021 · last 2026
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 5 since 2021
YearPublicationVenuePosition
2026 A 3.4-MHz Class-A Operational Amplifier in GaN Monolithic Technology with 80 dB Open-Loop Gain
Abhishek Joarder, Andrea Gambero, Sandro Rossi, Giulio Ricotti, Antonio Aprile, Edoardo Bonizzoni, Piero Malcovati
ISCAS2
2026 A 2.3-ns Response Time Temperature Insensitive Capacitive Level-Shifter with a Novel Active Pull-up for a 100-V Monolithic GaN Half Bridge
Tommaso Francesco Tardani, Andrea Gambero, Stefano Corona, Sandro Rossi, Antonio Aprile, Elisabetta Moisello, Giulio Ricotti, Edoardo Bonizzoni, Piero Malcovati
ISCAS2
2026 A 50-ns Response Time High-Side Current Sense with a Novel Analog Level-Shifting Technique for a 100-V Monolithic 1-μm GaN-on-Si Half Bridge
Tommaso Francesco Tardani, Andrea Gambero, Sandro Rossi, Antonio Aprile, Elisabetta Moisello, Giulio Ricotti, Edoardo Bonizzoni, Piero Malcovati
ISCAS2
2025 High Time-Resolution PWM generator for GaN Converters
abstract
High time resolution is key to get the most out of Gallium Nitride (GaN) technology in designing fast and high efficiency power converters. High resolution digital pulse-width modulation (DPWM) can be used, but it needs to be designed with a reasonable operating frequency to avoid high dynamic power dissipation. In this paper, a DPWM based on a programmable delay unit implemented in a closed loop solution is presented. The loop ensures that the elements in the delay chain have the same delay enabling PVT variation rejection and result consistency without the need for a high operating frequency. This allows tuning signals with a resolution of 195 ps and a high linearity, making the unit compatible with the requirements for driving GaN power devices. The system has been implemented in a test chip using 100 V 0.13 μm BCD technology at 40 MHz operating frequency and validated with a custom debug board that confirms the expected resolution over a wide tuning range.
Michelangelo Orabona, Stefano Passi, Andrea Gambero, Roberto Bardelli, Francesco D'Angelo
ISCAS3
2025 A 145-ns Response Time High-Side Current Sense for a 100-V Monolithic GaN Half Bridge
abstract
This paper presents a monolithic GaN current sense circuit designed for the high-side of a 100-V half-bridge. The circuit is engineered to minimize current offsets and response times across a wide range of input voltages (10 V to 100 V), as well as varying temperatures and current loads. It is capable of tracking inductor current ripples and detecting the zero-current condition of the half-bridge high-side power transistor. The proposed solution demonstrates a simulated loop gain exceeding 100 dB and a bandwidth of 43.9 MHz, which achieves an accuracy of 99.4% and a response time of 145 ns under operating conditions of 50-V input voltage, 10-A current load, and 27°C.
Tommaso Francesco Tardani, Andrea Gambero, Sandro Rossi, Antonio Aprile, Edoardo Bonizzoni, Piero Malcovati
ISCAS2