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Jinjin Hai

dblp:219/5065 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2026
0000-0002-3767-8152ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Distributed systems · 33%
Artificial intelligence
1 paper
Graph learning · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › circuit partitioning
hypergraph partitioning
1.012026
Hypergraph pseudo-label learning with neighborhood consistency for unseen netlist partitioning · Comput. Aided Des. 2026
Distributed systems › fault tolerance › failure models
network partitioning
1.012026
Hypergraph pseudo-label learning with neighborhood consistency for unseen netlist partitioning · Comput. Aided Des. 2026
Electronic design automation
physical design
1.012026
Hypergraph pseudo-label learning with neighborhood consistency for unseen netlist partitioning · Comput. Aided Des. 2026
Machine learning › Graph learning
hypergraph learning
0.312026
Hypergraph pseudo-label learning with neighborhood consistency for unseen netlist partitioning · Comput. Aided Des. 2026

Methods — techniques the papers use, named apart from their topics

pseudo-label learning · 2.0neighborhood consistency · 2.0
YearPublicationVenuePosition
2026 Hypergraph pseudo-label learning with neighborhood consistency for unseen netlist partitioning
Jie Yang 0053, Jian Chen 0025, Jinjin Hai, Xiangli Yang, Bin Yan 0002
Comput. Aided Des.4
2018 Wire segmentation for printed circuit board using deep convolutional neural network and graph cut model
abstract
Printed circuit board wire segmentation based on computed tomography (CT) image can help subsequently locate and estimate inner faults of circuit in an automatic and non‐destructive manner. However, CT imaging is prone to suffer from scattered artefacts, metal artefacts and other interference, destroying compact boundary structures of wires. Wires have the characteristic of dense local distribution, and massive vias, pads, and coppers can appear close to wires, resulting in mazy recognition surroundings. The above‐mentioned problems bring great difficulty for high‐accuracy recognition and location of wire segmentation. In this study, considering that deep convolutional neural network (DCNN) with powerful feature representation can recognise wires in confused surroundings, and graph cut (GC) model relying on grayscale and local texture information specialises in protecting edge structures of wires, the authors propose an effective framework called DCNN‐GC that employs DCNN to obtain global semantic prior to guide the GC model to accomplish satisfactory wire segmentation. The authors qualitative and quantitative results demonstrate outstanding performance, and achieve overwhelming intersection over union compared with traditional and DCNN‐based methods.
Jian Chen 0025, Jinjin Hai, Bin Yan 0002
IET Image Process.4