The quadrature phase clocks are important elements in digital programmable transceivers in communication system applications. However, current solutions in quadrature clock generators for broad frequency ranges need more phase accuracy, and they suffer from substandard phase noise performance and excessive power consumption. To address these challenges, this paper proposes an inverter-based quadrature-phase clock (I-QPC) generator. The I-QPC generator utilizes inverters as delay elements to achieve the desired phase without using poly-phase type-1 filters because inverters are simpler to design and optimize for different phase delays. The system implements a phase-averaging mechanism using the delayed and interpolated signals, leading to quadrature-phase signals. The proposed technique has been validated in 28nm standard CMOS technology after post-layout parasitic extraction. The I-QPC generator operates over the broad frequency range (1GHz to 6GHz) and occupies an active area of 0.0005mm2. The post-layout simulation results show that the phase error is ±0.29°while operating at 6GHz. The phase noise is -131.7dBc/Hz at an offset of 1MHz with a power consumption of 2.9mW. The I-QPC generator’s figure of merit (FoM) is 217.3dBc/Hz at 1MHz offset frequency, which is better than state-of-the-art architectures. The performance of the I-QPC generator was further evaluated in hardware by implementing the circuit on a breadboard using the SN74HC04N inverter IC, and it demonstrated the successful generation of the quadrature signals at 1MHz frequency.

Associative memory (AM) robustly retrieves information from given partial data. Compared to artificial neural network (ANN)-based AM, spiking neural network (SNN)-based AM offers greater bio-plausibility, sparsity, and message storage capacity. Recently, an ANN-based multidirectional associative memory neural network (MAMNN) for handling multiple associations was implemented by extending an ANN-based bidirectional associative memory (BAM) neural network. In comparison, this study implements SpiMAM, a more bio-plausible MAMNN based on SNN with a winner-take-all mechanism. The circuit design of spiking MAMNN (SpiMAM) employing in-situ synaptic training was proposed for the first time. Instead of a memristor device or memristor model, a CMOS circuit of a memristive synapse featuring spike-timing-dependent-plasticity (STDP) is used to incorporate the CMOS integrated circuit challenges. The synaptic weights in the crossbar for storage and association of patterns were trained on-chip without requiring additional computing platforms and digital circuitry attached to the synapse. The entire circuit of the spiking MAMNN was implemented at the transistor-level in 180 nm standard CMOS technology to demonstrate pattern recognition applications. The robustness of the proposed circuit of SpiMAM was evaluated through post-layout simulations for PVT, mismatch variation, pixel flip, hard faults, memristive drifts, and Gaussian noise. Compared to the previous work, this work uses 86 % fewer synapses and 70 % fewer neurons for the pattern recognition of nine binary images of$5\times 3$pixel size.

Spiking neural networks (SNNs) implemented in neuromorphic computing architectures promise a high degree of bio-plausibility and energy efficiency compared to the artificial neural network (ANN). Thus, SNN-based spiking associative memories are preferred for high capacity, area, and energy-efficient neural associative memories (NAMs). While most previously published works focused on ANN-based NAM, this work implements the full CMOS circuit of memristor crossbar-based spiking NAM for the first time. Instead of using any software-based memristive SPICE model or memristive devices that are yet not available in standard CMOS technology process design kits (PDKs), in our work, the CMOS-based memristive synapse circuit is employed to address practical circuit implementation challenges. The complete ON-chip learning of the system is demonstrated using the bio-plausible spike-timing-dependent plasticity (STDP) learning mechanism without employing any external coprocessor, e.g., microprocessor, field-programmable gate array (FPGA). The entire system is implemented at the transistor level using 180-nm standard CMOS technology to demonstrate the pattern recognition application. The robustness of the proposed circuit is also evaluated to demonstrate the tolerance against the CMOS fabrication non-idealities.

This paper presents an inductorless full rate pseudo-random binary sequence generator (PRBSG). Data rate of the PRBSG can be enhanced by 23% using internal pre-emphasis. The technique uses D flip-flops (DFFs) as 1-tap decision feedback equalizers (DFE) to equalize the outputs of the previous DFFs. This makes every DFF a DFE circuit, which is also used as a delay element for the PRBSG. The proposed technique increases the data-rate of the PRBSG significantly with minor increase in area and power. A design methodology to find the feedback factor of pre-emphasis technique using least square estimation is also presented. Post layout simulation in standard 90 nm CMOS technology of the 27-1 PRBSG confirms operation of the circuit at a data-rate of 13 Gb/s with peak to peak jitter of 8 ps, while consuming 222 mW off a 1 V supply, without using inductors.

Testing of high-speed Digital-to-Analog Converters (DACs) is a challenging task, as it requires large number of high-speed synchronized input signals with specific test patterns. To overcome this problem, we propose use of PRBS signals with an “Alternate-Bit-Tapping” technique and eye-diagram measurement as a solution to efficiently generate the test-vectors and test the DACs. This approach covers all levels and transitions necessary for testing the dynamic behavior of the DAC completely, in minimum possible time. Circuit level simulations are used to verify its usefulness in testing a 4-bit 20-GS/s current-steering DAC.